Why should a company dedicated to the success of Mixed Signal Virtual Components and Systems-on-Chip, with high resolution, low power consumption and high density, care about EDA Solutions?
⇒ To be the Leader of Innovative Design Flows, or rather Design "Chains", with efficient loops, top-down and bottom-up at every development stage.
And why care so much about multi-level simulation?
⇒ Because these circuits have to be Right-on-First-Pass and robust enough, taking into account dispersion effects to avoid yield drops or performance loss during mass production.
Designers are faced with an untractable situation where they need a lot of know-how and perform guess work for checking their real SoC.
SMASH is the reference Analog and Mixed-Signal (AMS), Logic and Mixed-Signal (LMS) and All-in-One Simulator enabling truthfully the combination of digital, logic and analog multi-domain modeling with no need for a “cosimulation backplane”, as well as Instruction Set Simulation (ISS).
Moreover, the extensive support of design kits and foundry model parameter sets is regularly enhanced with new and emerging SPICE device model implementations (Level 49, from BSIM 3 to BSIM 4v6, EKV, ACM, MM9, VBIC, MEXTRAM, JUNCAP2, PSP…).
Each of its successive releases contributes to reinforcing its unique features that make it the best for logic and mixed-signal (LMS) or multi-level and multi-domain designs:
⇒ Without the tweaking and twiddling required from foundries for so-called Golden simulators to make them look good, while most designers cannot trust their designs from their simulation results. SMASH is a must for Right-on-First-Pass designs.
Unique Capabilities
Providing All-in-One capabilities, as it supports all major hardware description languages (HDL), be they logic or analog (SPICE, Verilog HDL, Verilog-A, VHDL, VHDL-AMS, SystemC, C, ABCD) within a single kernel for simulation, SMASH is renowned as the fastest and most accurate simulator for VHDL-AMS models.
It offers unique and patented features to track design bugs, such as floating nets, and optimize your Design for Yield (DfY) with offset and dispersion analysis, as well as most relevant analyses (transient noise, jitter, phase noise, multiple operating point detection, …).
⇒ Don’t wait any longer to SMASH your bugs !
SMASH Constellation
SMASH is both framework independent and open to bridging with EDA tools for interoperability at different levels of the Design Chains.
SLED | Composer, Laker AMS
For access to schematics Any schematic capture able to generate a black-box based multi language netlist.
SLED more…
Composer, Laker AMS more…
SUCCESS | Raisonance's Ride, Keil's uVision
To co-simulate any microprocessor with its application program and any peripherals (logic and analog) more…
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