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Presentation Sheet

Multi-Level Equivalence Checking

 

Vector Files
Ascertainment of Equivalence
Templates

 

With the ever increasing complexity of integrated circuits and the integration of third-party blocks or Virtual Components, multi-level modeling and simulation is the only solution to reduce cycle-time of top-level simulations. The major difficulty in multi-level modeling is the checking required to verify a certain class of equivalence between models at different levels.

SMASH innovates for automatic multi-level equivalence checking with logic and analog templates using vector files.

Key Benefits

  • Direct use of vector file input signals as input patterns for analog or logic simulations
  • Configurable conversion of vector file signals to logic templates (hysteresis, timing accuracy…) or analog templates (delays, slope, smooth interpolation…)
  • Automatic ascertainment of equivalence for logic timing with on-line reporting of discrepancies between effective and expected outputs
  • Recording to vector files of selected input signals and expected outputs from analog or logic simulations
  • HSpice compliant support with extensions for increased flexibility of vector files

Logic and analog templates equivalent to the reference

Logic and analog templates equivalent to the reference

Description of the solution

Hard blocks, such as standard cells, memories, or analog IPs, are delivered in SPICE as well as a higher-level behavioral logic models for verification of the integration in the SoC. The challenge in using behavioral logic models at SoC level is to correctly prove the appropriate equivalences between the SPICE implementation and the behavioral logic models.
The multi-level equivalence checking innovation delivered by SMASH allows verifying a certain equivalence by applying the same input patterns on both models and checking that the outputs are equivalent to the expected outputs. The vector file (including input patterns and expected outputs) can serve as specification of the block, or can be captured by SMASH from an analog, logic or mixed-signal simulation. Thus, SMASH enables both top-down and bottom-up approaches for multi-level equivalence verifications.

In a top-down approach:

  • the vector file serves as specification; both the SPICE implementation and the behavioral logic model must have outputs equivalent to the expected outputs of the vector file,
  • the logic model serves as specification and is used to generate the reference vector file. Simulation of the SPICE implementation must have equivalent outputs.

In a bottom-up approach:

  • the SPICE implementation is the reference and is used to generate the vector file. Simulation of the behavioral logic model must have equivalent outputs.

 

 

 

Top-Down
Equivalence Checking
Bottom-Up

 

A typical example of top-down equivalence checking is for the integration of a Virtual Component in a SoC. The SoC simulation at top-level is considered as the reference. The behavioral logic model of the ViC is used to generate the vector file for equivalence checking with the implementation, whether SPICE, RTL logic, synthesized netlist...

TOP-DOWN EQUIVALENCE CHECKING

equivalence

Top-level simulation using a behavioral model of the Virtual Component captures input patterns and output signals to a vector file.

Any analog input patterns or output signals are converted to logic values according to designer specified waveform conversion characteristics.

 

 

The vector file format defines an equivalence class for timing verification, in transient analysis, of blocks with input/output signals that are of logic nature.

 

Implementation level simulation of the Virtual Component is driven by the reference input patterns from the captured vector file.

Ascertainment of equivalence is performed against the expected output signals with automatic conversion of logic expected outputs to analog waveforms as needed.

 

BOTTOM-UP EQUIVALENCE CHECKING

A typical example of bottom-up equivalence checking is for proving that a behavioral logic model of a cell or block is equivalent to its implementation. The implementation level simulation (SPICE, RTL logic...) is the reference from which the vector file is captured. With appropriate waveform conversion characteristics, the vector file is then used to verify the logic timing equivalence of the behavioral logic model.

 

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