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Verilog-A(MS) Modeling Training

 

A 2-day active training on Verilog-A(MS) modeling techniques

 

Microdul - Wilfried Hasselberg, IC Design Project Leader and Phil Poole, Director Semiconductor

Microdul

"Our team has benefited from the Verilog-AMS modeling training performed by Dolphin Integration at Microdul's office. We have particularly appreciated the short but consistent theoretical introduction which is then completed by concrete and complex exercises. The training was really oriented towards modeling techniques and not only towards EDA solutions. We are now efficiently prepared to start using this language for our next designs. We will for sure recommend it without hesitation to any person!"

Today’s Challenges

Systems-on-Chip (SoC) and systems integrate more and more analog and mixed-signal blocks with ever rising complexity. Full-SPICE simulations are no longer conceivable!
Behavioral models implemented in Verilog-A(MS) enable the designer to apply a top-down approach (e.g. for architecture definition) or a bottom-up approach (e.g. for circuit validation) to benefit from advantages such as:

  • delivering an executable specification at an early design stage,
  • enabling verification and optimization runs over the whole system in a mixed-signal simulator,
  • increasing simulation speed using behavioral models of selected components of the system.

 

languages of SMASH

Who should attend this training?

This seminar is intended for designers involved in mixed-signal electrical designs and/or analog behavioral modeling and simulation.

 

Why should you attend?

The optimal usage of an analog and mixed-signal language is complex since it does not only describe the model behavior itself, it also provides language constructs or commands for simulation synchronization between signal domain (event driven) and electrical domain (time continuous) entities. Having the necessary knowledge of mixed-signal simulation is crucial to succeed in multi-level modeling of mixed-signal designs. The training teaches you the techniques enabled by the Verilog-A(MS) language to master the modeling challenges in this field.
By attending this training, you will:

  • Acquire the fundamental knowledge of the Verilog-A(MS) language
  • Apply multiple modeling techniques (behavioral, structural)
  • Identify which applications benefit from a Verilog-A(MS) implementation

Prerequisites

Basic knowledge of the modeling functionality of some electrical components (resistor, diode…)

EDA solutions

SLASH, combining the schematic editor SLED and the mixed-signal multi-domain simulator SMASH.

Practical information

This training lasts 2 days during which theoretical information will be illustrated with examples. It can be led in English, French, German and Chinese.
Snacks, lunch and coffees are offered to the trainees.

 

Course agenda

DAY 1

Morning topics
Introduction to Verilog-A(MS)
This chapter will provide designers with a first overview of the language including mixed-signal modeling and simulation techniques with Verilog-AMS. The designers will also assess what is possible to do with Verilog-AMS compared to SPICE.

Verilog-AMS statement extensions to Verilog
This chapter will introduce the designer to the statements added to Verilog to enrich the event driven approach to continuous time and to the statements supporting the implementation of ordinary differential equations.

Afternoon topics
Time domain modeling
This chapter will teach how to perform time domain modeling, including initial conditions and handling of discontinuities.

Frequency domain modeling
This chapter will explain how to extract the magnitude and the phase of a signal depending on the frequency

DAY 2

Morning topics
Transfer function based modeling
This chapter will show how to replace filter circuits by a simple function representing its behavior for continuous and sampled systems.

Diverse VHDL-AMS specific modeling hints
This chapter will present how to use parallel branches to obtain the current of each branch and teach how to exchange data with file I/O.

Afternoon topics
Hierarchical modeling
This chapter will tackle two hierarchical modeling techniques: source level hierarchy for behavioral modeling and schematic level hierarchy for structural assembly.

 

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