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VHDL-AMS modeling techniques

A 2-day active training

Today’s Challenges

Systems-on-Chip (SoC) and systems integrate more and more analog and mixed-signal blocks. Proven top-down design methods for pure digital circuits can not be applied directly to mixed-signal designs where bottom-up design flows are generally used for analog components. Behavioral models implemented in VHDL-AMS enable the designer to apply a top-down approach also for analog and mixed-signal designs to benefit from advantages such as:

  • delivering an executable specification at an early design stage,
  • enabling verification and optimization runs over the whole system in a mixed-signal simulator,
  • increasing simulation speed using behavioral models of selected components of the system.

VHDL-AMS also eases the modeling and, therefore, the simulation of multi-domain systems including both electrical and mechanical, thermal, hydraulics, and/or magnetic models.

 

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Who should attend this training?

This seminar is intended for designers involved in mixed-signal electrical designs and/or analog behavioral modeling and simulation.

 

Why should you attend?

The optimal usage of an analog and mixed-signal language is complex since it does not only describe the model behavior itself, it also provides language constructs or commands for the simulation synchronization between signal domain (event driven) and electrical domain (time continuous) entities. Having the necessary knowledge of mixed-signal simulation is crucial to succeed in modeling mixed-signal designs. The training teaches you the techniques enabled by the VHDL-AMS language to master the modeling challenges in this field.
By attending this training, you will:

  • Acquire the fundamental knowledge of the VHDL-AMS language
  • Apply multiple modeling techniques (behavioral, structural)
  • Understand the mixing of VHDL-AMS capabilities in otherwise pure logic HDL models!
  • Identify which applications benefit from a VHDL-AMS implementation

Additionally, when creating a behavioral model for a specific device, there are many possibilities depending on the characteristics which need to be modeled. Therefore, designers must master the concept of equivalence classes presented during the training.
All practical exercises will be performed with SMASH, the simulator offering the best coverage of the VHDL-AMS standard.


Prerequisites

  • Basic knowledge of the modeling functionality of some electrical components (Resistor, Diode…)
  • Basic knowledge of VHDL

EDA solutions

SLASH, combining the schematic editor SLED and the mixed-signal multi-domain simulator SMASH.

Practical information

This training lasts 2 days during which theoretical information will be illustrated by one or several examples. It can be led either in English or in German. Snacks, lunch and coffees are offered to the trainees.

 

Become a VHDL-AMS modeling expert

DAY 1

Morning topics
Introduction to VHDL-AMS
This chapter will provide designers with a first overview of the language including mixed-signal modeling and simulation techniques with VHDL-AMS. The designers will also assess what is possible to do with VHDL-AMS compared to SPICE. The concept of equivalence classes will be explained so that designers get sensitized to identifying which device characteristics need to be modeled depending on the application.

VHDL-AMS statement extensions to VHDL
This chapter will introduce the designer to the statements added to VHDL to enrich the event driven approach to continuous time and to the statements supporting the implementation of ordinary differential equations.

Afternoon topics
Time domain modeling
This chapter will teach how to perform time domain modeling, including initial conditions, handling of discontinuities and time step control.

Frequency domain modeling
This chapter will explain how to extract the magnitude and the phase of a signal depending on the frequency.

DAY 2

Morning topics
Transfer function based modeling
This chapter will show how to replace filter circuits by a simple function representing its behavior for continuous and sampled systems.

Diverse VHDL-AMS specific modeling hints
This chapter will teach how to exchange data with I/O file, create function repositories with packages and generalize functions with operator overloading.

Afternoon topics
Hierarchical modeling
This chapter will tackle two hierarchical modeling techniques: source level hierarchy
for behavioral modeling and schematic level hierarchy for structural assembly.

 

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