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SMASH SVA

Assertion-Based Verification

Code Coverage

Debugger

 

 

The SMASH SVA option targets logic designers and opens the world of Assertion-Based Verification (ABV) with the support of the two major verification languages: PSL (Property Specification Language) and SVA (SystemVerilog Assertions). The integrated debugger and code coverage capabilities provide the features needed to debug and certify that design verification coverage is sufficient.

languages of SMASH

Key Features

  • Simulation of descriptions in SystemVerilog
    • Verilog-95, Verilog-2001 and SystemVerilog
  • State-of-the-art support of Assertion-Based Verification languages with PSL and SVA
    • Assemble verification units in the hierarchy
    • Embed assertions in the hardware descriptions
  • Hierarchical source-level debugger with breakpoints, watching, backtrace and event viewer
  • Code coverage analysis and reporting for models, instances, statements and conditions

Assertion-Based Verification

  • Assemble verification units in the design hierarchy
  • Embed assertions in the design descriptions
  • Detect hard to find bugs in much fewer lines of code than corresponding Verilog verifications
  • Verify complex temporal properties using immediate and concurrent assertions
  • View source code with syntax coloring

Assertion-Based Verification
TIMA

TIMA Laboratory - Techniques of Informatics and Microelectronics for integrated systems Architecture
SVA and PSL properties simulation based on the HORUS technology developed by the Verification and Modeling of Digital Systems (VDS) group at TIMA - http://tima.imag.fr/vds.

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Code Coverage
Debugger

Code Coverage

  • Tracking of untested portions of designs and algorithms in Verilog descriptions
  • Determination of how a set of test cases exercises the RTL code of a circuit
    • Global and focused coverage verification
    • Model and instance coverage
    • Statement coverage for lines, statements, blocks and branch decisions
    • Condition coverage for analysis of all possible outcomes of condition expressions
  • Analysis of coverage results with HTML reports
  • Identification of when detailed coverage was reached
  • Location of coverage problems and how to write test cases to solve them

 

 

 

Debugger

  • Hierarchical view of the design for fast and direct access to the source code
  • Isolation of design bugs by placing breakpoints on time, signals, source code, boolean expressions and temporal PSL properties
    • Enable step by step simulation,
    • Step over time points, delta cycles, events or instructions
  • Slow motion or animated mode simulation to help identify the cause of a design bug
  • Watching of variables, signals, quantities and expressions for online investigation of “data” and “calculation” design bugs
  • Simulation history, or backtrace
    • Online investigation of design “behavior” and “control” bugs
    • Determination of the data change paths in the simulation
  • Upcoming events viewer
    • Understand delta cycle problems in behavioral modeling
    • Make explicit the event execution order

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