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Custom Testbench/Training Package

 

The complexity of System-on-Chips (SoCs) and their integration as part of Chipsets require specific modeling expertise, especially in connection with Power and Clock networks.
Improving time-to-market with the confidence of mastering noise issues as propagated through the Power and Clock networks is critical for protecting high-performance Virtual Components (ViCs).

CTP

Through years of experience based on technical interactions with users in specific applications (Audio, Measurement…), Dolphin’s Central Application Engineers (CAEs) have acquired a deep understanding on “Hot Issues” happening at SoC and at Application level and have developed modeling skills to settle them by simulation.

What is at stake is to use the relevant models at the appropriate level of abstraction.

With our own Virtual Components (ViCs), our users benefit from specific deliverables for addressing hot issues to be dealt with:

  • JT2: Jitter Tolerance Template
  • THD vs Power Consumption
  • PSNT2: Power Supply Noise Tolerance Template
  • Audio data flow synchronization

ASC: Application Schematic for Configuration
ePMU: embedded Power Management Unit
CLK: clock generation path

 

 

To support our users complete safely and fast the integration of high-performance ViCs, the unique know-how developed by our Application Engineers is offered through two “CTP” products which may be acquired separately or combined:

CTP#1: Custom Training Package

It aims at transferring know-how on specific modeling techniques for safely embedding virtual components on SoC and in the user’s system with the appropriate DC-DC regulator network. It spells-out the solutions of concrete test cases with simulations needing to be mastered for the integration of such high-performance ViCs in the specific user context: JT2, PSNT2, CBTF…
This custom training is targeting both SoC Integration and Application Engineers and shall concretely train them in advanced modeling to ensure a successful integration.

CTP #2: Custom Testbench Package

It aims at providing Integration Hardware Models (IHM) and/or Application Hardware Models (AHM) and their Testbench to our users for them to handle the integration in connection with the hot issues identified in their specific SoC and Chipset context.
Such a CTP thus provides application engineers of our ViC users with adequate means to support their own customers.

 

For more information on the training program and the course description, contact the product manager Nathalie Dufayard at solutions@dolphin-integration.com