A move ahead towards Assertion-Based Verification with SLASH
Grenoble, France, December 11, 2009
With the autumn 2009 releases of SLASH, DOLPHIN Integration is delivering a significant upgrade for automating specification-based design verification techniques. Indeed, the bundle SLASH - schematic editor SLED coupled with mixed signal simulator SMASH – now natively supports Property Specification Language (PSL) assertions to empower designers for performing Assertion-Based Verification (ABV).
PSL is a language based on the Sugar language which originated at IBM Haifa. It has been IEEE standardized as PSL in 1995. It aims at specifying design properties through assertions to ensure that a circuit meets its specifications.
The designer or the verification engineer can instantiate PSL assertions in his design and simulate them for validation purposes with the relevant options of both SLED and SMASH. Moreover, the SLED ABV option enables to automatically generate synthesizable hardware checkers which can be embedded in a test chip, an FPGA, a secure circuit or a mission critical circuit for real-time monitoring. The generated RTL views of PSL properties (in Verilog or VHDL) can be easily integrated into any design environment.
You are now able to easily design circuits with embedded monitoring capabilities!
For more information on PSL, feel free to download the presentation sheet or contact Nathalie Dufayard at solutions@dolphin.fr
The free discovery options of SMASH & SLED are available for download
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