Dolphin Integration revolutionizes subsystem performance validation with Application Hardware Modeling
Grenoble, France, July 4, 2011
Every SoC Integrator talks about TTM and lower cost: at least, Dolphin Integration has taken-up this challenge!
The key is to anticipate, through Application Hardware Modeling (AHM), as early as possible, the integration issues affecting performances such as Jitter, Crosstalk, Yield, SNR degradation…
But Application Hardware involves devices on the PCB.
The integration of Silicon IPs, even with the highest resolution, is tricky!
Indeed, their final performance can be degraded by supply noise, on-board parasitic resistances, process dispersion… and for such disturbances, specified SoC performances are not met.
Focus on each SoC subsystem, namely each subset of components dedicated to one major function and configured for a specific application, involves from Silicon IP to electromechanical peripherals. The virtual Test of subsystem performances thus requires modeling SoC and PCB selectively: a wise choice of diverse abstraction levels is needed!
To sum it up, Application Hardware Modeling enables the selective simulation of a subsystem, as illustrated in the linked video
Dolphin Integration, both Silicon IP and EDA solution provider, is supporting its users to face the TTM and low-cost challenge not only with enhanced products, with detailed specifications highlighting profiles and templates, which serve for ensuring the proper matching of components, and with simulation models, but also with training for Behavioral Modeling and with Case-study Tutorial Products.
With such offering, Dolphin’s users are in the best position to develop right-on-first pass Systems-on-Chip and to define the best application schematics for reaching the target performances in each market segment with the best trade-off between Silicon area and Bill of Material.
For more information, do not hesitate to contact the Marketing Manager, Nathalie Dufayard, at solutions@dolphin-integration.com.
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