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DOLPHIN Integration complete their offering with high added value trainings

 

Grenoble, France, March 18, 2011

Facing the pressure of delivery schedules to provide right-on-first-pass Silicon IPs and Custom Systems-on-Chip (SoC) themselves, Dolphin Integration have developed techniques based on behavioral modeling to speed-up simulation and on detectors to reduce verification time and increase hierarchical verification coverage.
Now that these methodologies have proven their added-value, Dolphin is spreading these techniques externally and making them accessible to designers through training programs as follows:

  • HDL-AMS Modeling trainings not only teach the language constructs of either Verilog-AMS or VHDL-AMS, but also techniques to create and validate behavioral models. By attending one of these trainings, designers will learn how to perform bottom-up modeling through structural assembly of behavioral models for multi-level simulations.
  • Analog Detectors training is based on the EMBLEM Detectors library and teaches how to use an existing detector, how to assemble custom detectors and how to implement a network of detectors for automating on-line verification of analog designs. Detectors from EMBLEM Detectors can be used in simulation to reveal expected events, undesirable events or bugs in analog or mixed circuits, with respect to specifications which would otherwise be checked only at latest stages.

All trainings are built on practical exercises which will be performed with SLED, the hierarchical schematic editor, and SMASH, the multi-level simulator.

Training sessions are organized regularly around Europe, America and Asia. The next session is scheduled beginning of April in Germany for the VHDL-AMS modeling training. Registrations are almost over, fill in this form to be able to attend this session.

For more information on the training programs and on the calendar of the next sessions, please contact Nathalie Dufayard at solutions@dolphin-integration.com.

 

 

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