Leading-edge demonstration of Application Hardware Modeling for SoC Integrators and Application Engineers of Fabless suppliers
Grenoble, France, December 5, 2011
The mixed-signal Silicon IP and EDA Solutions provider announces the availability of demonstrators of the usefulness of Application Hardware Modeling (AHM) to ensure the performance of Silicon IP or IC at PCB/System level, as early as possible in the design and integration process.
The traditional approach, which consists in designing a Silicon IP or an IC without considering the Application Schematics of reference for the system, may lead to unexpected performance drops, impacting both Time-To-Market and RoI.
As an illustration, shCOD95.SP04-Helium2, a high-resolution audio CODEC, has been fully designed with SLASH, the multi-domain solution enabling simulation astride SoC and PCB. The performances of shCOD95.SP04-Helium2 - such as SNR, THD… - have been simulated with its Application Schematics of reference, taking into consideration the critical issues to be mastered such as Jitter, Pop-up noise, and Noise propagated through the power supply.
The correlation between the simulated results and the measurements on the characterization board, designed in accordance with the Application Schematics of reference, demonstrates the efficiency of Application Hardware Modeling to minimize Time-to-Market.
The multi-level and multi-domain capabilities of SLASH then allow Application Engineers of Fabless makers to rely on a powerful solution to support their users in the process of optimizing the Application Schematics of the system embedding the SoC.
In complement to SLASH, the company promotes a product offering for the design of Virtual Application Boards (VAB), which enables Application Engineers to benefit from know-how transfer for dealing with critical issues related to the optimization of Application Schematics.
Demonstrations of the efficiency of Application Hardware Modeling for both SoC designers and for Application Engineers will be provided during IP-SoC 2011 to be held in Grenoble on December 7 and 8.
They show how to fix integration issues such as Jitter, Pop-up Noise… but also how to optimize the cost of an application schematic for a given SNR target.
For more information on Dolphin Integration offering, meet us at our booth #15 at IP-SOC 2011 on December 7 and 8 held in Grenoble or contact Nathalie Dufayard at solutions@dolphin.fr
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