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SMASH 5.5 enriched with Verilog-A

 

Verilog-AMS benefits designers by allowing them to describe and simulate analog and mixed signal designs using a top-down design methodology as well as the traditional bottom up approach. Moreover, Verilog-AMS provides powerful structural and behavioral modeling capabilities for systems in which the effects of, and interactions among, different disciplines like electrical, mechanical and thermal are important.

SMASH 5.5 extends its natively mixed-language and mixed-signal single kernel to Verilog-A with seamless hierarchical mixing with SPICE

 

Key enhancements

  • Verilog-A for micro-electronic designs
  • Mixed SPICE-AMS hierarchical circuit descriptions
  • Compiled Verilog(-AMS) models for IP protection
  • Automatic dependency handling and library recompilation as needed
  • Tracing of Verilog variables
  • Verilog-95, 2001 & AMS compliant parser with Verilog-2001 compatible preprocessing
  • Command Line Interface (CLI) to Verilog-AMS compiler ready for future batch scripts
 smash 5.5

 

Description of the compliance

In addition to already supported description languages, a Verilog-A subset targeting micro-electronic designs is now supported by SMASH. This subset supports mixed-signal multi language transient analysis of conservative and signal flow systems with:

  • Natures, disciplines and nets
  • Analog signals and contribution statements
  • Time derivative and integral analog operators
  • @cross monitored events
  • Environment parameter functions
  • Standard definitions of disciplines & constants

Furthermore, SMASH provides natural use of library statements (.LIB) for specification of Verilog and Verilog-A libraries of modules. Dependency handling is completely automatic, thereby freeing the designer from manual recompilation of modified descriptions. Furthermore, the compiled “black-box”modules can be used directly and even delivered pre-compiled, for instance for evaluation purposes, thereby providing IP protection.

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