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SMASH 5.13

Interface Devices

Mixed SPICE & Verilog-A

Hierarchical Tolerances

 

The design and verification of systems, integrating ever more features, increases the complexity of Virtual Tests needed to check that specifications are met. Multi-level verifications have become mandatory to ensure right-on-first pass designs of multi-domain systems. Each part of the system must be modeled at the appropriate level, with the adequate hardware description language, depending on the required accuracy for measurement of characteristics.
SMASH 5.13 increases the flexibility for mixing hardware description languages and provides straightforward configuration of hierarchical tolerances.

 

Key features

  • Extended capabilities for mixed-signal interface devices with hysteresis, delay to X, interconnection of multiple logic signals…
  • Flexible hierarchical tolerances on different nets or parts of the circuit depending on the target accuracy and speed trade-off
  • Optimized Verilog-A behavioral model handling with tolerances and multi-processor support
  • Power-Up analysis for mixed-signal circuits
  • Input and output .VEC digital vector files, including HSPICE compatibility
  • Time precision handling for logic and mixed-signal simulations longer than 9223 seconds
  • Verification of PSL properties using the simple subset with mixed-signal extensions
  • Optimized SPICE library parsing for ten-fold reduction of circuit loading time when using statistical model parameter sets
 smash 5.13

 

Description of the ease of use

Mixing hardware description languages, such as SPICE, Verilog, Verilog-A, VHDL and VHDL-AMS, inevitably entails mixed-signal simulation, with logic and analog models, multi-level simulation, with structural and behavioral models, or multi-domain simulation.

  • Mixing analog and logic signals requires inserting interface devices for conversion of the signals. The single-kernel engine of SMASH has always delivered push-button mixed-signal simulation with automatic insertion of interface devices. These devices are enhanced to provide even more flexibility in the control of the conversion with hysteresis, delay to X…
    More information on Interface Devices...
  • Multi-level simulation requires handling different accuracy settings for best accuracy and speed trade-offs. The flexible support of VHDL-AMS tolerances in SMASH has been extended to SPICE and Verilog-A. Tolerances specified by the designer in Verilog-A models are now handled in the same manner as for VHDL-AMS. Furthermore, specific SPICE tolerances can also be specified on different nets or parts of the circuit. Whatever the analog description language used, be it SPICE, Verilog-A or VHDL-AMS, accuracy can be tuned in the hierarchy to help convergence and increase simulation speed.

 

 

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