Communication
Contacts
Offering
Investors
Careers
Libraries of Standard cells and Memories
Logic virtual components
Analog virtual components
Test structures
 Hardware/Software Codesign
Virtual test & diagnostic
 Hardware/Software Codesign
Layout verification
My MEDAL
Quadrant of skills
SoC Integration
Custom Fabless Supplier
 
 

Search dolphin:

SMASH 5.12 Increased Speed & Capacity

 

SMASH 5.12 enhances its leadership position with functionalities for Logic and Mixed Signal (LMS) as it now satisfies two crucial requirements for the SoC Integrator:
It provides new circuit monitoring capabilities, akin to real-time "Detectors", leveraging on-line and conditional expressions, supervised by an "Expression Watch Panel"!
It simultaneously provides a significant improvement for the capability of Virtual Testing thanks to Homotopy based heuristics for detection of multiple operating-points.

 

Key enhancements

  • Multi-core aware equation evaluation for SPICE device models to speed-up the analog simulation
  • Automatic detection of multiple operating-points to ensure design operation for all bias points
  • Improvement of Virtual Test capability with Homotopy based heuristics for the search of operating-points in addition to existing heuristics
  • Simplified use of audio data files with import to drive analog simulation and for waveform display, and export from transient simulation results
  • Time precision handling for VHDL and VHDL-AMS simulations longer than 9223 seconds
  • Enhanced debugger with expression watches, expression breakpoints and breakpoint actions
  • Verilog-2001 negative timing checks along with increased circuit loading capacity
  • User selection of which SPICE device and model parameters to output to the operating-point file
  • Enhanced find and replace in built-in text editors
  • SPICE flavor compatibility improvements for temperature parameter and nested sub-circuits
smash 5.9

 

Description of the ease of use

Enhancing the “detector” capabilities, and on the roadmap towards assertions, the integrated debugger now provides evaluators for expressions which can either be watched or used as breakpoint conditions to monitor circuit operation. Expressions can be composed of signals, quantities, arithmetic and comparison operators, logic operators in Verilog syntax, and common Verilog functions. When watched in the "Expression Watch Panel", they are updated automatically during simulation as well as whenever a pause occurs, whether caused by a breakpoint or by a user request.

Expression Breakpoints will pause the simulation whenever the associated expression becomes true. Breakpoints can be assigned a condition that will cause the breakpoint to be skipped when the condition is false, as well as a counter that can be used as a filter depending on the occurrence count: they serve as "Conditional Detectors". In addition, breakpoints can also be used as “trace points" for non-interactive debugging.

 

< SMASH Evolution over time

download SMASH