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SMASH 5.11 Efficient Mixing of Blocks
Performing true mixed-signal simulations, as needed by a growing proportion of SoCs, requires bringing together analog blocks, from a schematic based analog design flow on a purely analog simulator, and logic blocks, from a batch based HDL design flow on a purely logic simulator. As the mixed-signal simulator for SoCs, SMASH provides both the analog and logic capabilities to directly simulate with the original models, while adding the circuit and testbench setup capabilities needed to perform complete mixed-signal simulations.
SMASH 5.11 delivers enhanced ease of simulation setup and analysis while simplifying reuse of analog blocks with HDL in mixed-signal simulations!
Key features
- Enhanced ease of setup with simulator control file (.pat, .cir, .sp) for analog and logic designers
- Streamlined graphic user interface with reworked menu bar and enriched tool bars
- Extended formula editor dialog for creation of calculated traces
- Integrated Power-Up analysis for transient ramp-up of circuit power supplies
- Simplified and accelerated automatic operating-point searching for painfully converging circuits
- Bias point saving during transient analysis at designer specified times
- Extended noise analysis to Verilog-A models
- Support for encrypted SPICE libraries including .PROTECT related directives
- Integration of BSIM4 v6/v6.1 and PSP HSPICE extensions for increased compliance with foundry model parameter files
- Optimized on the fly SDF annotation to reduce memory consumption during circuit elaboration
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Description of the ease of use
The new tree display of the hierarchy above illustrates the granularity of mixing analog and logic at any level in the circuit hierarchy.
From an analog designer’s point of view, ease of use requires direct use of fab model parameter sets, loading of SPICE netlists whatever the flavor (Hspice, Eldo, Pspice…), fast and automatic operating-point convergence and probing of nets for waveform tracing. To this, SMASH adds unique circuit debugging features, such as dynamic ERC, dispersion sensitivity analysis… making it the best magnifier for bug-tracking.
From a logic designer’s point of view, ease of use requires straightforward compilation of HDL sources (possibly by converting compilation scripts from other solutions), simple setup of source code debugging for step by step simulation, probing of signals for efficient circuit state investigation, and code coverage reporting to ensure an exhaustive test coverage.
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