Communication
Contacts
Offering
Investors
Careers
Sesame
Embedded memories
Logic virtual components
Analog virtual components
Test structures
Hardware/Software Codesign
Virtual test & diagnostic
Hardware/Software Codesign
Layout verification
Quadrant of skills
SoC Integration
Custom Fabless Supplier
 
 

Search dolphin:

# 7 - Bottom up calibration for multilevel truthfulness and secured designs

 

Three calibrations are at stake:

  • with measurements on silicon for transistor models and parameters
  • with extractions from layout for electrical netlist back-annotations
  • with simulation results from any level for a higher level model

 

TEST CASE: Read Margin of a memory

First calibration: HORIZONTAL from silicon to transistor models
calibration
IDS Current Drain Source

VDS Voltage Drain Source

VGS Voltage Gate Source

BSIM4 model gives the equations which describe the behavior of the transistors

Calibration provides the parameters for adjusting those equations

Second calibration: TOPOLOGICAL from layout to netlist upwards

topological calibration

Based on experience the designer extracts manually some parameters from the layout such as subtract injection, coupling between bit-lines… to introduce in the electrical netlist.
Then a next step should be to perform the same operation with silicon measurements:
back to step 1.

Once the Spice models and the electrical netlist are calibrated vs layout and silicon, the simulation results can be representative of the physical reality.
Analyses, such as Monte-Carlo, can be performed in SMASH with the guarantee of the results on silicon.
Moreover, using Monte Carlo with this calibration technique, yield of the circuit can be predicted with a higher accuracy than with a single test chip!

smash

Third calibration: MODELING upwards, from process descriptions on to electrical -> structural -> functional -> behavioral -> system

modeling calibration

The electrical simulation is used to calibrate a behavioral simulation.
This behavioral simulation will be faster and will allow SoC level simulation.

SMASH

 

Beyond calibration

While multi-level zooming requires calibration for a memory “Read margin” or for ensuring that complex chains of transistor models truthfully represent silicon, some multi-level issues raise problems beyond zooming:

  • Laplace or s-transforms are powerful structural representations for continuous-time or analog implementations of filters and other devices with a linear functionality: but they can be embedded within the electrical models in SPICE, as well as within the behavioral models in VHDL,
  • Their discrete-time counterparts, the celebrated z-transforms serve for digital filters: but they can be implemented at the functional level, synthesizable into fixed logic at the gate level, as well as programmed in C to be executed by a DSP (Digital Signal Processor). Worse then: probably, because these circuits process analog inputs, the z-transform absurdly is only accessible as part of VERILOG-A or VHDL-AMS. This is in complete contradiction with the VSIA objective of Black-Box modeling, whereby even mixed signal circuits processing mixed-signal inputs should be modeled in pure VERILOG!
    The ultimate calibration issue.
  • Worse then, the celebrated Schmitt Trigger: look for its model in a SPICE library of devices! It is the paradigm of a mixed signal device thought by many to be a logic component, but dealing with analog inputs. As a matter of fact, it acts like a sense amplifier with the ReadMargin issues!

 

< SMASH Differentiators