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Equivalence checking with SMASH

 

Specification-driven verifications | Top-down and Bottom-up | Selective modeling | Template checking

 

Equivalence checking for multi-level verifications

With the ever increasing complexity of integrated circuits and the design of systems, whether mixed-signal or multi-domain, multi-level modeling is the only solution to reduce cycle-time of top-level simulations. One of the major difficulties for silicon IP designers and application engineers performing multi-level modeling is ensuring that models of different levels are equivalent with respect to a specific subset of the specification.

SMASH innovates by offering features for a streamlined equivalence checking user experience!

 

DEFINITION of Equivalence Checking

In the domain of circuit design, a specification describes the characteristics, or properties, that a design must meet along with the description of the tests that must be applied to verify these requirements. Models of a design are considered to be equivalent when they meet the same subset of a specification.

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Conformity of effects or behaviors is specified using templates which define the “border”. A template generally defines the minimum and/or maximum admissible values, in time domain, frequency domain… but can be more complex (such as the eye diagram). The template is the reference! It can be another model, measurement data or values extracted from a datasheet. A template implies an associated measurement method. If the model respects the templates for a selected subset of the specification and a given accuracy, the equivalence is proven.

KEY BENEFITS of Equivalence Checking

  • Use of different abstraction level models for selective multi-level verifications
  • Automatic and dynamic comparison between
    • Two models
    • A model and measurement data
    • A model and datasheet information
  • Easy identification of template violations thanks to visual display and warning reports
    • Violation identifications issued as soon as they occur: no need to wait until the end of the simulation
    • Equivalence checking in batch mode: no need to be in interactive mode
  • Simplified testbench validation and reuse by integrating the specification requirements directly in the testbench

KEY FEATURES for multi-level equivalence checking in SMASH

  • VEC Files for logic signals (HDL, SPICE)
    • Used for timing, signals shapes…
  • .measure directive for analog signals (HDL-AMS, SPICE) and analog results (FFT, Jitter…)
    • Used for SNR, THD, Jitter, power supply noise…

 

.measure directive

The .measure directive is generally used by analog and mixed-signal designers for characterization purposes. In SMASH, this directive can also be used for equivalence checking by comparing a measure result to a reference template.
In this case, the reference template can be specified from:

  • An other model
  • A specification set-up in a table based data file (.dat)
  • A measurement extracted in a table based data file (.dat)

For each performance, a margin (min / max) is expressed to define the template.

Application example

POINT DETECTION

 

Top-down equivalence checking between an HDL-AMS behavioral model of an amplifier and its SPICE implementation

Template = behavioral model +/- 30dB

No violation is detected!
The SPICE implementation is equivalent to the behavioral model with respect to the amplifier transfer function


 

POINT DETECTION

 

What happens with a more constrained template?

Template = behavioral model +/- 10dB

The template is violated!
The SPICE implementation and the behavioral model are not equivalent with respect to the amplifier transfer function.

The SPICE implementation must be improved or the specification requirements must be relaxed if they are too strict!


 

VEC files

VEC Files are traditionally used to generate voltage supply (PWL, pulse). In SMASH, their use has been extend to equivalence checking. They can detect template violations and glitches.

In a top-down approach:

  • the vector file serves as specification; both the SPICE implementation and the behavioral logic model must have outputs equivalent to the expected outputs of the vector file,
  • the logic model serves as specification and is used to generate the reference vector file. Simulation of the SPICE implementation must have equivalent outputs.

In a bottom-up approach:

  • the SPICE implementation is the reference and is used to generate the vector file. Simulation of the behavioral logic model must have equivalent outputs.

 

Application example

Equivalence checking between two transistor-level implementations of a logic function (clock tree generator) developed for migration purpose

application example

A glitch is detected!

The second implementation generates a glitch which can be disastrous when used in a clock tree.
Both implementations are not equivalent and the second one must be improved!

Attend the Behavioral Modeling Prerequisites Training
to learn how to create models and perform equivalence checking