SMASH™ your LMS Bugs! Improve your design yield
Eradicate design defects and weaknesses causing yield drops
Design methods and EDA solutions must ensure that design is not the cause of yield drops during fabrication. Traditional approaches are based on worst case analysis which result in adding margins, thus increasing area or reducing performances.
Recent technological processes have made this approach obsolete as electrical and topological dispersions become paramount: worst case design is no longer acceptable! Traditional simulations do not provide the appropriate functionalities needed to address this challenge.
With SMASH™ benefit from an arsenal of innovative features to win the war against design failures:
Key Benefits
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To guarantee design robustness with respect to statistical parameter variations
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To accelerate diagnostic of yield losses in fabrication
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Flexible integration of electrical or topological variations from foundry data
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Automatic detection of “Multiple Operating-Points” to ensure design operation for all bias points
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“Sensitivity Locate” to identify the contribution of each device to on-chip dispersion
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“Imbalance Locate” to diagnose design yield losses due to process dispersion
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“High Impedance Nets” detection to avoid mal-functioning circuits, yield losses, excessive leakage power…
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“SHAKER” for iterating simulations on process worst cases and worst conditions
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Fast and easy setup HDL and HDL-AMS source code debug and coverage analysis
Don’t miss your real target!
Design weakness identification
Original & efficient solutions
Multiple operating point detection
SMASH proposes the capability for multiple operating-point searching! It can automatically search for and find multiple (in most cases all) operating-points of a circuit.
With the operating-point analysis, SMASH proceeds through a complete search, using all heuristics in sequence, and gives the first stable result that is found. With multiple operating-point analysis, SMASH helps the designer to determine whether operating points are multiple and to identify meaningful ones in order to simplify eradicating unwanted operating-points which render the circuit useless when self-biased in such operating conditions!
Locate Sensitivity to on-chip dispersion
Mismatch sensitive devices
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Identify them
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Quantify the risk
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Act on it
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No Monte Carlo needed!
Can’t afford Monte Carlo for offset simulation? Use sensitivity to on-chip dispersion with SMASH!
“On-Chip dispersion” is defined as variations of characteristics between two identical devices, inside the same chip, after fabrication, with the result of matching issues.
Delivering the Sensitivity Locate analysis, SMASH provides unique capabilities for fast sensitivity to on-chip dispersion diagnostic without the burden of lengthy Monte Carlo analysis.
Increase your design power
with Accurate analysis
Automatic diagnosis of analog weaknesses and bugs
SMASH enables thorough diagnostic of circuit bugs causing yield losses and precise pinpointing of Imbalance Sensitivities!
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It diagnoses yield losses and provides efficient solutions to identify and then optimize transistors, resistors or capacitors sensitive to random dispersions such as mismatch effects,
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It allows designers to detect sensitive combinations of such devices by locating the imbalanced sets!
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Thanks to its patented SWIFT simulation mode, SMASH can deliver the results from a Monte-Carlo analysis two to three times faster than simulators using a conventional Spice algorithm.
Hi-Z Nets Detection
Hi-Z, also known as high impedance, tri-stated, or floating, is the state of a net or output terminal which is not currently driven by the circuit. High impedance nets are useful when used appropriately. However, unintentional high impedance nets are a frequent cause of non-working circuits while practically undetectable with functional simulations.
SMASH provides the analysis capabilities to detect these high-impedance nets.
To detect potentially crippling high impedance nets, SMASH provides an automated impedance analysis that identifies them during simulation based on a designer specified impedance threshold.
SMASH extends functional simulation to include an analog net “coverage like” analysis allowing to analyze impedance variation, measure capacitive and resistive net impedances and detect high impedance nets.
Methodology of Design-for-Yield
to increase Robustness
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