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SLED 1.5

 

Hierarchical

Design Rule Checker

PSL Assertions

 

Third generation Schematic Link Editor, SLED, helps increase designers’ productivity with graphic link and configuration entry for plugging assertion-based checks and easing hierarchical verification. As verification takes most of designers’ time, this release of SLED increases design robustness while decreasing verification time thanks to assertions in PSL (Property Specification Language) and efficient Design Rule Checks.
SLED 1.5 improves design robustness and enhances the design verification process!

 

Key enhancements

  • Quick localization of design problems through user configurable Design Rule Checker
  • Schematic link editing of PSL verification units for simulation or for embedded hardware monitoring
  • Enhanced mixed-language design using blocks described in SPICE and Verilog, in addition to VHDL
  • Integrated handling of Verilog for automatic symbol generation and netlisting
  • Streamlined property management with display focused on relevant properties
  • Extended possibility to create several views for the same cell (symbol, schematic, SPICE, VHDL, Verilog…)
 graphic SLED

Description of the benefits

The bundle SLASH of SLED and SMASH natively supports the synthesis and simulation of PSL assertions. Logic designers can graphically link PSL assertions of the expected behavior into the design. These can then be simulated jointly in SMASH to detect bugs earlier, or to locate faster the causes of problems.
Furthermore, the SLED-SDG option provides the means to generate synthesizable hardware checkers in Verilog or VHDL from PSL assertions. These checkers can then be embedded into an FPGA, a testchip, a secure circuit or a mission critical circuit for monitoring purposes. The generated hardware monitors can be used in any design flow.

For increased designer productivity, SLED delivers enhanced property management enabling to add selectively properties to libraries, cells, symbols and instances. The values of properties can be propagated and the user can define on which objects the value of a property is editable. Mandatory properties can be defined with no default value: values are then required on the instance. Libraries, cells, symbols and instances contain and display relevant properties only.

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Improve verification time at the design stage with the Design Rule Checker

 

Designers fed up with long verification time and tired of discovering design problems at the end of the design flow, or worse after fabrication, will appreciate the new Design Rule Checker delivered in SLED.
In only 3 simple steps, it is possible to configure the rule checker, locate potential problems and correct them!

Improve verification time at the design stage with the Design Rule Checker

 

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