Plug’n Play into Cadence
Users of the Cadence framework and of its Composer schematics editor benefit directly from the unique capabilities of SMASH for exhibiting and locating design defects by simulation of analog as well as logic and memories, and indeed of mixed signal designs, even for an original circuit designed piecemeal.
COACH is the driver for mixed-signal hierarchical netlisting from the Cadence Composer schematics entry to SMASH and comes as an add-on to SMASH options, most appropriate for verification-intensive SoC Integration.
- Mixed-language netlisting from Cadence Composer
- Incremental netlisting using Simulation Environment
- Direct netlisting of “Cadencelike” Design Kit views
- Parameterized sub-circuit calls
- Batch mode netlisting
- Property based selection for netlisting as Verilog or SPICE
- Exploitable “single file” netlists
- Support for Cadence 4.4.6 or later under Solaris and Linux
Description of the ease of use
Integrated into the Cadence schematics entry, COACH netlisting control and operations are reached through the standard menus of Cadence Composer and Simulation Environment (SI).
This driver COACH provides:
- Mixed-language (SPICE & Verilog) and mixed-signal incremental netlisting both interactively and in batch mode,
- Cross-probing for selection of nets in Cadence SI to display the appropriate waveforms in SMASH,
- Use of Cadence views (hspiceS, cdsSpice, verilog, behavioral) for standard Cadence-like design kits that provide these views,
...once the original design is netlisted to SMASH, exploiting the unique features provided by SMASH is easy:
- Automatic management of mixed signal netlists with no arcane settings,
- “dynamic Electrical Rule Checks”(dERC) to perform electrical integrity checks of a circuit to verify that circuit variables do not exceed predefined limits,
- “Imbalance Locate”for thorough diagnostic of circuit bugs causing yield losses and for precisely pinpointing Imbalance Sensitivities.
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