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Description |
Overview
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Download |
| System Level |
COSMOS |
Cosimulation of mixed-signal and system-level blocks coupling SMASH with MATLAB / Simulink |
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SUCCESS |
Hardware/Software co-design coupling SMASH with Ride or µVision |
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SLED |
Hierarchical Schematic Editor with dual capability for Graphic Entry and for Scriptability |
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SMASH |
Multi-domain mixed-signal simulator for behavioral modeling of systems in HDL-AMS |
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VDALIBS |
VDA automotive libraries packaged in SLED with symbols and SMASH |
pending |
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EMBLEM Math |
Library of general mathematical functions for system design |
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EMBLEM Mecha |
Library of fundamental effects for MEMS modeling (VHDL-AMS) |
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EMBLEM Drive |
Library of fundamental effects for DC-motors modeling (VHDL-AMS) |
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EMBLEM Detectors |
Library of fundamental elements for custom detector assembly and ready-to-use detectors to ease validation |
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| SoC Integration |
SLED SDG |
Automatic generation of synthesizable RTL modules from assertions (PSL/SVA) |
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SCROOGE TLA |
Hierarchical mixed signal power consumption estimation with clock-tree emulation and SPEF back-annotation |
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SMASH |
Multi-domain mixed-signal simulation for subsystem performance optimization and validation |
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SoC GDS |
VSIA socket generator for hierarchical SoC Integration of Virtual Components |
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| IP / IC Design |
SLED |
Hierarchical Schematic Editor with dual capability for Graphic Entry and for Scriptability |
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SMASH |
Mixed-signal multi-language simulator for mixed modeling of ASICs in SPICE, Verilog-HDL, VHDL… |
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| Characterization |
SHAKER |
Simulation iterator for automatic characterization and datasheet extraction |
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SMASH |
Mixed-signal simulator for characterization of ASICs in SPICE, Verilog, VHDL… |
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| Backend Layout |
SoC GDS |
Fast layout viewer and processor for structured layout and advanced verification (GDS II, OASIS, OA) |
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GDS Compiler |
Development platform for layout array generator development |
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| Mask Shop |
GDS Reticle |
Constraints based frame layout placement optimizer for scribe line test structures |
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