Communication
Contacts
Offering
Investors
Careers
Sesame
Embedded memories
Logic virtual components
Analog virtual components
Test structures
 Hardware/Software Codesign
Virtual test & diagnostic
 Hardware/Software Codesign
Layout verification
Quadrant of skills
SoC Integration
Custom Fabless Supplier
 
 

Search dolphin:

silicium estimator

 

THE ODYSSEY OF SESAME LIBRARY

 

Block-busting

Reduced Cell Stem Library

HD - LC - HS - ULL optimizations

 

 

SESAME, A REDUCED LIBRARY FOR INCREASED PERFORMANCES

SESAME has benefited from the initial developments made by the CSEM (Swiss Electronic and Microtechnic Center) since 98 for the ultra-low-power demanded by the watch industry.
Proposed since 2004, SESAME takes advantage of Dolphin’s 20 years of expertise in the design of embedded memories while relying on a unique and stringent qualification process. It led to enhancing the ultra-low power features of SESAME with major innovations in the directions of low power, low-leakage, high density, high speed, low voltage and Time-to-Fab. There is more to come for reducing congestion…

 

SESAME, A PROVEN RECORD OF CONTINUOUS INNOVATION

Odyssey

 

Continuous innovations for

Less power
less leakage
smaller area
faster place and route…

 

Resulting in The 5 Advantages of the SESAME library

the 4 advantages

 

KEY MILESTONES

2004

  • Launch of the SESAME product line resulting from the CSEM partnership based on the first and second advantage
  • First industrial partnerships for low voltage and low power for LP1 Library
  • Patent on a specific D-flip-flop which is less sensitive to clock edges and guarantees the functionality at very low voltage.

2005

  • Second generation of LP library named eLCvHS, re-optimized for better density with same low power and low voltage

2006

  • Launch of the first ultra-high density stem uHD
  • Design wins for low-power in 0.18 and 0.25 µm
  • Second release of uHD library, enhanced for higher speed with same low area benefits
  • First design wins for ultra-high density

2007

  • Licensing agreements with Tier1 companies and leading foundries
  • Launch of BIV library for Battery Interface Voltage range
  • Launch of low-power libraries for 130 and 90 nm

2008

  • Launch of retention islet project (upon prospects’ requests)
  • Design wins in 90 and 130 nm
  • High-density BTF library for common platform at 65 nm
  • Back-Tracking Freedom, a capability which eliminates the disruptive iterations for fixing timing-critical paths
  • Referencement by TSMC for ultra high density and ultra low power at 180 nm

2009

  • Launch of HD-BTF in 65 nm and 180 nm
  • Patent-pending enhancement by “STI-Stress Freedom” for high density and high speed in the most advanced process nodes

2010

  • Launch of the improved release of HD-BTF in 65 nm, 130 nm and 180 nm with the "spinner cell”
  • Stem composition with the HS-BTF stem in 65 nm, 130 nm and 180 nm
  • Launch of the Dual Voltage release of the HD-BTF in 180 nm