3A for Back-Tracking Freedom
The challenge for SoC designers is to obtain the optimal die size, speed and power in the minimum amount of time.
Problems with competitors’ traditional offering:
A methodology of a new kind had thus to be created: the Melpomene way (named for a mythological Muse).
Based on the knowledge of the ARSA (Asymptotically reachable SoC Area), Melpomene enables to choose an adequate P&R duration for an acceptable area and constraints of IR-drop, etc. The area target is based on a 2- step SoC complexity analysis: upon synthesis, and after a first pass Raw P&R.
But how could any predictive methodology be possible without control over the iteration loops?
Traditional libraries offer no control on the load capacitance when the cell drive increases. As a result each modification in a critical path impacts all the paths upstream!
With SESAME BTF the cells are separated from drives with the constraint of input capacitances equal for all drives.
A designer can choose to replace any function or drive on a critical path in order to meet the performance targets, without the penalty of any need for adaptation of the nets upstream. A local improvement no longer disturbs the rest of the paths!
Moreover, non-critical paths may be optimized for another objective: dynamic power or leakage.
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