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silicium estimator

 

Best with... 130 nm HIGH DENSITY PANOPLY

Memories
Register Files
Standard Cell Libraries

 

To maintain or increase their strength on the market, manufacturers of high density consumer and nomad devices must regularly offer more features to their end customers - while maintaining competitive pricing. Because of this trend, finding the best compromise between low power and cost reduction is a significant challenge for SoC designers.
The solution is introduced with a complete Panoply optimized for High Density and Low dynamic Power.
The panoply includes Single Port and Dual Port RAMs, metal programmable ROMs, Register Files and standard cells.

 

Haumea: a common architecture for Single Port RAM and Dual Port RAM of medium instance capacities

The Haumea architecture is THE optimal mix between low dynamic power consumption and density.

 

KEY BENEFITS OF THE spRAM HAUMEA

Macro CELL SYMBOL
  • Decrease of fabrication costs
    • Up to 20% denser than alternative solutions
    • 1P3M with routing allowed from metal 4 and above
    • Rotatable memory
  • Decongestion
    • Innovative power line structure
    • Routability of 100% on M4
  • Power reduction features
    • Up to 50% less consuming than alternative solutions
    • Data retention mode
    • Stand by mode
    • Flexible power routing: power ring or ring-less
    • Byte write/read capability
    • Innovative design to minimize power consumption
  • Optimal DfY
    • Read margin optimized instance by instance

 

KEY BENEFITS OF THE dpRAM HAUMEA

Macro CELL SYMBOL
  • New innovative functionality
    • Read and Write operations can be performed jointly at the same address on both ports allowing a full asynchronous access (no timing constraint between clocks)
  • Decrease of fabrication costs
    • Ultra high density thanks to the patent pending access strip: 50% denser than traditional dpRAM!
    • Designed with the uHD bit-cell from foundry
    • 1P3M with routing allowed from metal 4 and above
    • Mixable in the logic blocks among the rows of the density optimized standard cells HD-BTF
    • Rotatable memory
  • Power reduction features
    • Ultra low leakage: 10 times less leaky than traditional dpRAM!
    • Ultra low dynamic power: 40% less consuming than traditional dpRAM!
    • Byte write/read capability
    • Data retention mode

 

Architectural implementation with the High density-Low Power panoply

Selecting separately the smallest Silicon IPs from different providers does not guarantee the achievement of the highest overall density SoC: for instance the area savings of high-density sRAM could be offset by a bigger regulator caused by higher dynamic power consumption!
To assist SoC Integrators in their permanent search for minimizing costs, Dolphin Integration offers a complete panoply of memories, register files, standard cells and their associated regulators. This panoply is designed to ensure the best individual density of each component and efficient integration to allow maximal area savings when combined in the same SoC.

 

Integration for the best density

Density optimized power supply network

Choosing the appropriate “cascade” of regulators optimized for the best efficiency ensures the longest battery operation and the highest density:

  • Reduced power consumption allows to embed regulators using internal flying caps
  • Reduced dynamic power consumption minimizes the size of the power grid: the routability of the highest metal layers is increased
  • Depending on applications the selection of a cap-less embedded regulator ensures a lower Bill-Of-Material
  • Embedding a tailored power management regulator allows to reduce the cost of the external Power Management Chip
  • Regulators can be efficiently placed near the pads (from the battery and for the output capacitance)
  • M5 and M6 may be selected for the power grid

Density optimized placement and routing, and testing

  • The largest ROM and RAM are placed near their respective regulators to optimize the distribution of the peak of currents and power grid, with the smallest impact on routing
  • The Panoply is designed with the smallest number of metal layers:
    • Only M1 is used for cell design of SESAME so that at least 3 levels are available for routing (1P4M)
    • Routing over the Haumea and Aura instances starts from metal 4
      • spRAM is 100% M4 free
      • Register Files are an average of 50% M4 free
  • The Panoply is designed to facilitate the multiple use of small memories:
    • The ins tances of Aura can be placed freely in the logic block by the P&R tool to fill free spaces:
      • Aura topology is a multiple of SESAME pitch to allow abutment with standard cells
    • Free rotation at R0, R90, R180, R270
  • The Dolphin BIST-Aura is designed to minimize the additional area required for the test.
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