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65 nm High Density Panoply

Reducing the silicon costs is a permanent concern for SoC Integrators. This cost challenge can only be addressed at the architectural level with a complete solution for all elements of the logic design.
The solution is introduced with a complete Panoply optimized for High Density.
The Dolphin Integration 65 nm High Density Panoply is designed for consumer and industrial applications with high fabrication volumes and low cost manufacturing requirements.
The panoply includes Single Port and Dual Port RAMs, metal programmable ROMs, Register Files and standard cells.

130 nm High Density Panoply

Reducing the silicon costs is a permanent concern for SoC Integrators. This cost challenge can only be addressed at the architectural level with a complete solution for all elements of the logic design.
The solution is introduced with a complete Panoply optimized for High Density.
The Dolphin Integration 130 nm High Density Panoply is designed for consumer and industrial applications with high fabrication volumes and low cost manufacturing requirements.
The panoply includes Single Port and Dual Port RAMs, metal programmable ROMs, Register Files and standard cells.

130 nm Dual Voltage Panoply

To satisfy demanding customers, Fabless companies are facing the need to embed always more features in their chip. The increasing complexity of SoC results in both an increased silicon area and an increased power consumption. To be efficient, power management must be managed at the architectural level.
To facilitate power optimized implementation, Dolphin Integration is introducing a Panoply of Memories, Registers, Standard Cells and regulators which uniquely offer Dual Voltage capability and are delivered with characterizations for 1.2 V and 0.9 V in the 130 nm G process node.