Standard Cell Benchmark
Reliable evaluation process
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And after sales integration solutions
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For standard cell designs
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Any Standard Cell library must be accompanied with integration guidelines, and evaluated when used accordingly. Arguing on details separately in the SESAME specifications misses the point, so that the list of cells is controlled as an ISO-9001 procedures for its RCSL structure and the ensuing circuit architecture is protected by pending patents.
The BTF control and data paths for SESAME stems are different from those with a classical library, the clock paths are different from those in any CCSL library. At their intersections, the spinner cells are different from flip-flops. The only common points are the standard EDA solutions (Synthesizer, Placer, STA and Router).
The crucial reason for such adamant differentiation of our SESAME stems can be understood when margins are taken into account to ensure yield in presence of mismatch. Standard cell evaluation suffers from the lack of comparative and public databases to assess the comparative performances of truly different RCSL and CCSL.
As the promoter of Reduced Cell Stem Libraries (RCSL) Dolphin Integration provides all standard cell users with a step by step benchmarking process besides the irrelevant comparison between NAND2s.
Step one: Discovery of the SESAME RCSL library
Collaterals
Depending on the stem, different types of collaterals are freely available on our website to discover more about the features and benefits of a SESAME library: the presentation sheet, the brochure, a description of the benchmarks.
Step two: Assessment of performances of the SESAME RCSL library
Sofia benchmark
The Sofia benchmark is as easy as the traditional NAND2 but far more representative as it is based on a sample of six cells representative of a typical design including a sequential cell. Sofia results is a figure of merit comparing the dynamic power consumption, area, leakage and speed after synthesis of different libraries. For more information on the Sofia benchmark, click here
Motu Uta logic Standard
For a complete comparative evaluation of libraries from synthesis through Placement to Routing, the Motu Uta logic standard (logic block in RTL) is proposed. Made public as freeware, Motu Uta embeds a processor, different critical paths (register-decoding-register, register-ALU-register) and combinatorial logic, representative of a typical logic block in all dimensions: area, power consumption and speed, while avoiding mistakes due to the misreading of a proprietary standard. Motu Uta is a public logic standard, with free download access.
Thalie heuristic formula
Thalie serves to evaluate the Asymptotically Reachable SoC Area “ARSA” for Motu Uta with each library. To assess the minimum area reachable in an infinite time, Thalie proceeds through various estimates of parameters describing the logic block: result of a logic synthesis, estimation of number of flip flops… For more information on the Thalie heuristic formula, click here
Step three: After Sale Integration with the SESAME RCSL library
Delivery of the library
While any Cell library should benefit from its own integration guidelines, it took until SESAME RCSL to address this need explicitly so that Dolphin Integration FAEs are currently introducing the essential guidelines enabling customers use Sesame RCSL in the most efficient way.
Thalie heuristic formula
Thalie serves to evaluate the Asymptotically Reachable SoC Area “ARSA” for a given design with the SESAME library.
Thetis
Comes the time of actual integration and the Thetis formula serves to estimate the area achievable with the SESAME library for a given design, given an allowance of the time to spend at Place & Route.
Thoe
SoC Integrators need to be able to estimate easily the time to spend on a design at Place & Route to achieve a targeted area with any library but the SESAME library is favored by its BTF structure.
You can benefit from free support from our FAE and know how on Reduced Cell Stem Library all along your evaluation process.
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