Flash announcement
Dolphin Integration concentrates on cost-cutting with the Standard Cell Library HD-BTF for 65 nm processes
Meylan, France – May 7, 2010
Fabless companies can seize the opportunity to decrease the area of their logic blocks by 5 to 10% with the highest-density Standard Cell Library available in the 65 nm technological process!
Reducing silicon costs is a permanent concern for SoC Integrators targeting applications with high fabrication volumes, especially with the care needed for mismatch resilience. Given the increasing complexity of logic designs in advanced process nodes, and the ever growing size of logic blocks, embedding a “cost-cutting” Library is now committed.
To facilitate cost-optimized designs, the Dolphin’s 65 nm High Density Library, HD-BTF is the solution of choice.
HD-BTF indeed is a real star for cost reduction with 5 to 10% higher density than typical 7 tracks standard cell libraries after P&R:
- 6 track library
- High Density Spinner cell for reduced sequential area
- Density optimized cell layout and placement of pins
- Delivered with the “4 season scripts” for an automated optimization at each step of the implementation flow
More information on the key benefits and performances of HD-BTF is available directly on the link below:
http://www.dolphin.fr/flip/sesame/65/sesame_65_HD_BTF.html
Skeptical Standard Cell would-be Users can easily benchmark this Standard Cell Library against any other with the Sofia Benchmark and the Motu Uta public standard, so they must feel free to visit our website:
http://www.dolphin.fr/flip/sesame/sesame_benchmark.php
or contact sesame@dolphin.fr
The High-Density Panoply including a complete solution for all elements of the logic design is also available to address the cost reduction challenge at the architectural level.
The panoply includes Single Port and Dual Port RAMs, metal programmable ROMs, Register Files and standard cells.
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