Flash announcement
An ultra High Density Library decreasing the 130 nm logic area up to 30%
Meylan, France – June 14, 2010
Designers of cost-optimized SoC designs can rely upon the highest-density Standard Cell Library, HD-BTF to improve the area of their logic blocks with a decrease up to 30%.
Compared with typical 9 tracks library after P&R, HD-BTF make easier the quest for density:
- 6 track library
- High Density flip flop: the Spinner cell system for reduced sequential area
- Density optimized cell layout and placement of pins
- Delivered with optimization scripts for each stage of the implementation flow: from Synthesis, through Placement and construction of the Clock paths to Routing.
Density remains the Holy Grail for many SoC Integrators, but they tend to rely on stale scripting techniques. Indeed, from the 130 nm process node, the increasing complexity and size of logic blocks forces SoC integrators to concentrate more than ever on tuning their designs with high leverage. This challenge is even more noticeable for applications with high fabrication volumes such as mobile phones. Achieving a cost effective SoC by embedding a “cost-cutting” Library is now the last frontier.
More information on the key benefits and performances of HD-BTF is available. Please click here.
Benchmarking this Standard Cell Library against any other now is easy with the Sofia Benchmark and the Motu Uta public standard, visit our website,
or contact sesame@dolphin.fr
A High-Density Panoply including a complete solution for all elements of the logic design is also available to address the cost reduction challenge at the architectural level.
The panoply includes Single Port and Dual Port RAMs, metal programmable ROMs, Register Files and standard cells.
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