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Thalie
Formula |
To compute the Asymptotic Area of a design |
The smallest silicon area achievable for a given design remains a question mark for the majority of designers.
Dolphin Integration names this smallest achievable area the “Asymptotically Reachable SoC Area “ or “ARSA”.
The Real Reachable SoC Area will depend on the ARSA, but also on additional constraints (e.g. form factor) and the time budget allocated to the Place and Route (see “MELPOMENE”). The first release of Thalie formula is dedicated to the ARSA evaluation of a logic block.
This Presentation sheet introduces “Thalie”, the formula to estimate the ARSA for a given logic block with any library. Thalie can estimate ARSA starting from various parameters describing the logic block (result of a logic synthesis, estimation of number of flip flops…). The accuracy of the estimation will depend on the accuracy of the input parameters.
Key Benefits of Thalie
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Easy area estimation of a specific logic design
Less than 30 minutes needed
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Universal formula
ARSA can be applied for any library
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Support from Dolphin Integration
Access to the ARSA result of the Dolphin library stems on Motu Uta
Evaluation of the ARSA result of the Dolphin library stems on the user design
Engineering support provided all along the evaluation process
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Content
The formula is based on 3 elements:
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Total Standard Cell area
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Clock tree area
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Routability
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Evaluation Process
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Licensor and user must adopt one benchmarking context (design,process, technological node,…), with realistic constraints (frequency…).
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Each team then completes the evaluation for assessing the ARSA: the one with your current library and the one with Dolphin Integration library stem
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Both parties share the results and compare the reported data.
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