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Presentation Sheet

SESAME HD BTF rel 1.2 90 nm LP

 

 

High Density stem

Back-Tracking Freedom capability

Both for Cost reduction

 

A LIBRARY FOR COST REDUCTION!

The diversity of process derivatives and providers for the 90 nm technological node strengthens the inclination of engineering teams to attempt reducing the Time-To-Market and the risks related to a SoC design by either selecting their usual Silicon IP Provider or “free libraries”. This development strategy narrows the potential profits of a chip as the risk to select an average performances library is increased. Dolphin Integration expands the options of SoC designers with the HD-BTF Standard Cell Library. Already celebrated for its cost reduction capability, due to its RCSL (Reduced Cell Stem Library) structure, the HD-BTF Library is specifically designed for the consumer industry, targeting area sensitive applications with high volume of fabrication. The HD-BTF Library additionally enables fast migration to any process flavors or technological node. Thereby, SoC designers can easily target any optimized set of process options to guarantee the best RoI.

 

Key benefits

  • High density
    • Up to 10% smaller area compared to the best high density alternatives
    • Split of Spinner Buffer from Clock Gating enabling a faster clock tree synthesis while ensuring higher density
    • High Density Spinner Cell
  • Low dynamic power
    • Up to 30% less consuming, to reduce the costs of system cooling and power supply component and improve heat dissipation
  • Back-Tracking Freedom
    • Capability that eliminates the disruptive loops for fixing timing-critical paths
    • HD BTF innovatively combines the separation of the drives from the logic functions with the constraint of an equivalent input capacitance for all drives
    • Gain in density and power consumption with speed preservation
    • Superior for Time-To-Fab rendered predictable and fast
  • High routability
    • Only Metal 1 is used in layout

Product Features

  • Operating voltage: 1.2 V +/-10%
  • Innovative evaluation process thanks to representative benchmarks
  • High design yield and reliability thanks to a thorough Virtual Fab Process™
  • Level Shifter (VDD <-> VDD) included, other characterizations provided as add-on
  • Inductor-less regulators provided as add-ons to reduce the Bill of Material
spider 90 nm

Deliverables

  • Datasheet (ASCII)
  • Specification (pdf)
  • Use manual (pdf)
  • Simulation models (VHDL/Verilog Tetramax compatible)
  • View for Synthesis including Timing Analysis Model, Power models and WLM (.LIB and .db)
  • Flattened Netlist for LVS (Spice)
  • Footprint (LEF), antenna LEF and process LEF
  • Detailed Physical Block Description (GDSII)
  • Milkyway Database

 

 

stamp

SoC ROUTING allowed upwards from Metal1
Compatible with 1P3M SoC
Best performances with 1P5M SoC

 

 

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