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Presentation Sheet

Sesame eLCvHS 250 nm

 

 

extremely Low power Consumption

very High Speed

 

 

The rising demand for battery-powered and RF applications requires library providers to offer innovative solutions based on new design techniques to lower the overall power consumption of a SoC.
SESAME uLC 2.5 addresses this need by dramatically reducing power consumption compared with other solutions, while offering the possibility to operate at very high speed.

SESAME uLC 2.5 is the optimal solution for markets like Medical, Wireless, Mobile Phone, RFID, Smart Card or Portable Multimedia!

 

Key benefits

  • Reduce the power consumption of your SoC up to 60% thanks to standard cells optimized for low-power at the schematic level
  • Patent for uLC 2.5 => reduction of power consumption through decreased sensitivity to clock edge and delay variation
  • High speed optimized architecture for critical designs: up to 20% faster
  • Improved routability: clever I/O pins placement and use of only 1 metal layer inside the cells
  • High design yield and reliability thanks to our Virtual Fab Process™
  • Assess the benefits of our SESAME stems thanks to our “Try and Buy” evaluation tutorial
spider 250 nm

 

Deliverables

  • Datasheet (ASCII)
  • Specification (pdf)
  • Simulation models (VHDL/Verilog Tetramax compatible)
  • View for Synthesis including Timing Analysis Model and Power models (.LIB and .db)
  • Flattened Netlist for LVS (CDL)
  • Footprint (LEF), antenna LEF and process LEF
  • Detailed Physical Block Description (GDSII)
  

Add-ons

  • Integrated Clock Gating Cells
  • Flip-flop with asynchronous set and reset
  • Falling edge flip-flops

 

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