SESAME LVLC 250 nm
extremely Voltage Scaling |
very High Density |
Reducing the overall power consumption of a SoC while minimizing costs has become critical issue for SoC designers, especially for battery-powered applications.
Voltage Scaling has become a promising technical approach to reduce dynamic power consumption in deep submicron technological processes. Indeed, the capability of a library to work at very low voltage enables important power savings: dividing the voltage by 2 enables to reduce dynamic power consumption by 4!
SESAME uLC 1.2, optimized for extremely low power through Voltage Scaling while preserving a high density, adresses the need for voltage scaling solutions also in mature technological processes.
Key benefits of SESAME LVLC
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Increase the battery-life of the end product: divide the dynamic power consumption of your SoC by up to 6 thanks to standard cells schematic optimized for low-power and to the low voltage capability
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Reduce the costs of IC packaging, system cooling and power supply components
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Reduce silicon costs thanks to high-density
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Shrinkable to 0.22 µm
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Assess the benefits of our SESAME stems thanks to our “ Try and Buy” evaluation tutorial
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Key Features
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Already available for 0.25 embedded Flash and 0.25 logic processes
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Patent for low voltage operation => decreased sensitivity to clock edge and delay variation
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Power supply voltage range from 1.2 to 2.75 V
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High design yield and reliability thanks to our strict Virtual Fab Process™
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Key Applications:
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RF applications
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Medical
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Smart cards
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Mobile storage devices
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Deliverables
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Datasheet (ASCII)
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Specification (pdf)
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Simulation models (VHDL/Verilog Tetramax compatible)
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View for Synthesis including Timing Analysis Model and Power models (.LIB and .db)
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Flattened Netlist for LVS (CDL)
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Footprint (LEF), antenna LEF and process LEF
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Detailed Physical Block Description (GDSII)
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Add-ons
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