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Presentation Sheet

SESAME uHD BTF rel 1.2 TSMC 180 nm G

High density stem

Back-Tracking Freedom capability

Both for Cost reduction

 

 

A library for cost reduction!

Cost reduction in mature technological processes requires that IP providers take divergent paths: high density with standard design rules is a must, but Place and Route also is reduced by Back-Tracking Freedom.
The SESAME HD library is already celebrated for its twofold cost reduction capability in the standard processes 0.18 and 0.13 µm G, due on the one hand to its RCSL (Reduced Cell Stem Library) structure and on the other hand to its BTF capability (Back-Tracking freedom). Additionally it is now enriched Power Islets for mere Extinction or with Retention.
The HD stem is particularly fit for applications like multimedia players, USB controllers, RFID and GPS/PDA.
SoC designers can now benefit from the availability of SESAME HD also in shrunk processes at 0.16 and 0.152 µm G.

Key benefits

  • High density
    • Up to 20% smaller area compared to the best high density alternatives
    • Split of Spinner Buffer from Clock Gating enabling a faster clock tree synthesis while ensuring higher density
    • High Density Spinner Cell
  • Low dynamic power:
    • Twice less consuming, to reduce the costs of system cooling and power supply component and improve heat dissipation
  • Back-Tracking Freedom
    • Capability that eliminates the disruptive loops for fixing timing-critical paths
    • HD BTF innovatively combines the separation of the drives from the logic functions with the constraint of an equivalent input capacitance for all drives
    • Gain in density and power consumption with speed preservation
    • Superior for Time-To-Fab rendered predictable and fast
  • High routability
    • Only Metal 1 is used in layout

Product Features

  • Operation voltage: 1.8 V +/-10%
  • Innovative evaluation process thanks to representative benchmarks
  • High design yield and reliability thanks to a thorough Virtual Fab Process™
  • Level Shifter (VDD <-> VDD) included, other characterizations provided as add-on
  • Inductor-less regulators provided as add-ons to reduce the Bill of Material

 

spider 180 nm

 

Deliverables

  • Datasheet (html)
  • Specification (pdf)
  • Use manual (pdf)
  • Simulation models (Verilog Tetramax compatible)
  • View for Synthesis including Timing Analysis Model, Power models and WLM (.lib and .db)
  • Flattened Netlist for LVS (Spice)
  • Footprint (LEF), antenna LEF and process LEF
  • Detailed Physical Block Description (GDSII)
  • Milkyway Database
 soc routing

SoC ROUTING allowed upwards from Metal1
Compatible with 1P3M SoC
Best performances with 1P5M SoC

 

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