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The quest for The “ROM Benchmark”

 

To demonstrate the kind of alternative benchmark that would be complete from our point of view and readily applicable by anyone, while straightforward, our best guess is provided below as a complete and rather reasonable set of answers.

- Some examples of simple ROM Benchmarks -

A - Dynamic power consumption

For Process, Voltage, Temperature and cload output, refer to each product.

 

The "Hot ROM Benchmark"

Temperature (25°C)
100% are active Read cycles
50% of the address bits are switching
50% of the Data Output bus bits are always switching
Memory plane is programmed with a uniform distribution of the y x-bit words

  

The "Cold ROM Benchmark"

Ambient temperature (25°C)
50% are active Read cycles
Address bits are increased one by one
25% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words


The "Cool ROM Benchmark”

Temperature (37°C)
70% are active Read cycles
All low significant address bits are switching
50% of the Data Out bus bits are switching
Memory plane is programmed with a uniform distribution of the y x-bit words

  

 

 

Other parameters play a role for reducing the dynamic power-consumption:
  • Read Margin: it can be more or less reduced but at the expense of yield.
  • Data IN/ Data OUT Bus: does the figure for power consumption take the output bus capacitance into account?
  • Frequency: the more favorable case is when power consumption is computed at a frequency corresponding to the cycle time!

 

B- Dynamic NOP (No OPeration) power consumption

100 % of clock cycles are inactive, clock signal is active
50% of the address bit are switching, at each clock cycle,
other input signals are at a static level (VSS or VDD).
The memory is powered on.

 

C- Power consumption from Stand-by leakage

Neither data transfers nor clock signals are active, and the select signal is Off.
All input signals (including the clock signal) are static at level VSS or VDD.
The memory is powered on.
This standby leakage consumption comes from the leakage of transistors mostly and diodes.
It is computed on the VDD power supply by simulation:
Memory is deselected on one cycle, then Stand-by power consumption computation is performed after a delay of several hundred of nanosecond.
This figure truly reflects the memory operation, better than pure computation from mean-value of leakage on both n and p type transistors.

 

D - Dynamic static consumption

Benchmark Violet- "Standby mode"

VDD_in = standard voltage as per technological process
Memory initialization for one cycle (CSN = 1)
Then no variation of the input signals (including clock)
Integration of the leakage current after waiting for the stabilization of the internal nodes
and current