To demonstrate the kind of alternative benchmark that would be complete from our point of view and readily applicable by anyone, while straightforward, our best guess is provided below as a complete and rather reasonable set of answers.
- Some examples of simple RAM Benchmarks -
A - Dynamic power consumption
For Process, Voltage, Temperature and cload output, refer to each product.
The "Pessimistic RAM Benchmark"
Ambient temperature (25°C)
100% are active cycles (50% WR, 50% RD)
50% of the address bits are switching every cycle
50% of the Data Output bus bits are always switching with Cdout = 0 pf
Minimum cycle time
Memory plane is programmed with a uniform distribution of the y x-bit words
The ”Hot RAM Benchmark”
Temperature (25°C)
100% are active cycles (20% WR, 80% RD)
3 lowest address bits in incremental mode +only one big toggle at each operation cycle (Gray code)
50% of the Data Output bus bits are always switching with Cdout = 0 pf
Memory plane is programmed with a uniform distribution of the y x-bit words
The "Cold RAM Benchmark”
Ambient temperature (25°C)
50% are active cycles (25% WR, 25% RD)
3 lowest address bits in incremental mode
50% of the Data Output bus bits are always switching with Cdout = 0 pf
Memory plane is programmed with a uniform distribution of the y x-bit words
The "Cool RAM Benchmark”
Temperature (37°C)
70% are active cycles (45% WR, 25% RD)
3 lowest address bits in incremental mode + only one big toggle at each operation cycle (Gray code)
50% of the Data Output bus bits are always switching with Cdout = 0 pf
Memory plane is programmed with a uniform distribution of the y x-bit words
B - Dynamic NOP (No OPeration) power consumption
100 % of clock cycles are inactive, clock signal is active
50% of the address bit are switching, at each clock cycle,
50% of the data input bits are switching at each clock cycle,
other input signals are at a static level (VSS or VDD).
The memory is powered on.
C - Power consumption from Stand-by leakage
Neither data transfers nor clock signals are active, and the select signal is Off.
All input signals (including the clock signal) are static at level VSS or VDD.
The memory is powered on.
This standby leakage consumption comes from the leakage of transistors mostly and diodes.
It is computed on the VDD power supply by simulation:
Memory is deselected on one cycle, then Stand-by power consumption computation is performed after a delay of several hundred of nanosecond.
This figure truly reflects the memory operation, better than pure computation from mean-value of leakage on both n and p type transistors.
D - Dynamic static consumption
Benchmark Green - "Sleep mode" or "Data retention mode"
VDD_in = 0, VDD_co = standard
voltage as per techno
No variation of the inputs
Integration of the leakage current after waiting for the stabilization of the bits lines
Benchmark Violet - "Standby mode"
VDD_in = VDD_co = standard voltage as per technological process
Memory initialization for one cycle (CSN = 1)
Then no variation of the input signals (including clock)
Integration of the leakage current after waiting for the stabilization of the internal nodes
and current
Benchmark Red - "Standby mode" for some specific products
Static power consumption is measured on a cycle duration with deselection of memory
(CSN active) between several Read/Write cycles -> very pessimistic benchmark
All input signals (including the clock signal) are static at level VSS or VDD.
This standby leakage consumption comes from the leakage of transistors mostly an
diodes
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