Flash announcement
A new Panoply of Silicon IPs for reducing the 65 nm silicon area up to 10%
Meylan, France – June 25, 2010
Designers of cost-optimized SoCs now can take advantage of the High Density Panoply to increase the density of their SoC up to 10%.
The Dolphin Integration High Density Panoply for the 65 nm technological process comprises a complete solution for the whole logic design to address the cost reduction challenge at the architectural level.
The HD Panoply integrates:
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The 6 track Standard Cell Library, HD-BTF
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The Aura architecture for One Port and Two Ports Register Files from 128 bits up to 32 kbits
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Single Port and Dual Port RAMs Haumea from 16 kbits up to 512 kbits
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Metal Programmable ROMs from 1kbit up to 6MBits known as the Haumea and Phoenix architectures
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Application and Integration support to ensure the highest density at SoC level
The High Density Panoply is a real star for cost reduction:
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Depending on the instance capacity, the spRAM Haumea is up to 15% denser than contender’s solutions
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Embedding the patent pending Access Strip, the dpRAM Haumea is up to 30% denser than traditional dpRAM
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Thanks to the patented “two-in-one” high density bit-cell, instances generated with the Phoenix architecture for ROM are 2 times smaller than alternative ROM
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The Aura architecture for Register Files is designed to be mixable in the logic blocks among the rows of the Standard Cell Library
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The Standard Cell Library HD-BTF is 5% to 10% denser than a typical 7 track Standard Cell Library after P&R
Do you feel skeptical about the achievement of such performances on your own design? Contact us to take advantage of our suggested Application Schematics, Prescriptions and Consistency of Products for a density-optimized architecture:
ragtime@dolphin.fr
More information on the key benefits and performances of the High Density Panoply is available directly on the Brochure:
Please click here.
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