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Flash announcement

Library portfolio at 65 nm

 

Meylan, France – September 21st, 2009

Dolphin Integration focuses on providing users with a full offering featuring embedded memories and standard cells of diverse optimizations for the 65 nm process node.

So-called « free libraries » with average performances are a good solution for very low volumes, but as long as high fabrication volumes are concerned, only the best performance tradeoff can guarantee the winner’s RoI.

Dolphin Integration broad offering at 65 nm enables designers to select any tradeoff between dynamic power consumption, area, speed and leakage, with the objective to address the needs of various applications in the consumer, communication and automotive markets.

Dolphin Integration 65 nm portfolio includes:

  • 3 robust architectures for memories introduced in the following order: Haumea for large dense instances, Aura for small capacities and Rhea for high speed.
  • 3 similar optimization criteria concern separate stems of standard cells: high density, then high speed and ultimately low power. All three stems offer Back-Tracking Freedom for a predictable and faster P&R in the shortest Time-to-Fab.

The compromise between power consumption and density constitutes the optimal balance for consumer applications. Designers on consumer markets can benefit from the features of the Haumea architecture for RAM and ROM, together with the high-density stem HD-BTF.

  • Haumea offers up to twice as little power consumption than competitive solutions: for example 15.470 uA/Mhz for a 8kx32 instance, while maintaining the same density at SoC level.
  • The HD-BTF stem achieves amazing performances: up to 15% denser and 30% less consuming than traditional alternatives.

The high-speed stem HS-BTF combined with the sRAM Rhea is being released. These products target applications such as Set Top Boxes or data-cards. These libraries are optimized to allow high-speed operations:

  • The sRAM Rhea achieves a speed of up to 600 Mhz worst case, while decreasing power consumption.
  • The HS-BTF stem is more than 40% faster than the high-density alternative HD-BTF.

Memories of small capacities are always critical for the overall performances of a SoC whatever the application. Register files are under development under the name of Aura with the objective to serve the major need for SoC Integration.

Dolphin Integration also offers extensions for low leakage with a Power Extinction and Retention Kit “PERK” for designing Power Islets , also enabling dynamic Energy Reduction.

Dolphin Integration is rolling-out, month after month, a series of innovations.
Information about the roadmap and about the latest releases of memories and standard cells is available on request, including options for low voltage designs.

For more information about Dolphin Integration 65 nm portfolio

 

 

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