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Flash announcement

Complement of our 130 nm catalog with a low voltage release of the ROM Cassiopeia

 

Meylan, France – November 13, 2009

The patented Cassiopeia architecture for single via programmable ROM is enriched with a capability to operate from nominal voltage down to 1.1 V , both +/- 10%, in the TSMC 130 nm LP process.

Cassiopeia is an architecture already celebrated for attaining low power consumption at nominal voltage on applications such as RFID or high-end mobile. Engineers seeking to maximize power savings can take advantage of the low voltage capability of Cassiopeia: reducing the voltage from 1.5V down to 1.1V results in more than twice further power savings!

Endowed with Dolphin Integration’s “Two in One” Patent, Cassiopeia is not only a low power ROM, but also a dense ROM. Cassiopeia is up to 20% denser than contenders, which enables SoC designers to benefit from an impressive decrease of fabrication costs.

Thanks to the success of Cassiopeia, already in mass fabrication in the TSMC 130 nm process, Dolphin Integration grants the capability to migrate to other foundries starting with SMIC.

The on-line Cassiopeia generator demonstrates flexibility to generate instances of ROM between 1Kb and 1 Mb.

For more information about the Cassiopeia architecture or to gain access to the Cassiopeia online generator for benchmarking purposes

 

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