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LOGOS standard for in-SoC area evaluation

 

 

Innovative evaluation process

for fair comparison

of memory performances

 

THE AREA OVERHEAD PARADOX

Basing the area assessment for memory instances only on compiler outputs can only result in hedged density, as it does not take into account the in-SoC area overhead.
For this reason, the area from the sRAM Haumea compiler versus competitors’ memory compilers leads most often to an apparently higher density for competitor’s, whereas the Haumea in-SoC area is far better than competitors’ embedding overhead.
As the promoter of standards for evaluating the comparative performances of competing libraries, Dolphin Integration addresses the challenge of in-SoC area assessment with the LOGOS standard.

 

THE LOGOS STANDARD FOR IN-SOC AREA ASSESSMENT

The in-SoC area overhead of the memory must be taken into account to avoid any density illusion. The following capabilities are thus considered with LOGOS:

  • The routing constraints
  • The impact of the Power supply methods (power rings, strips or embedded power supply)
  • The number of metal layers used by the memory
  • The number of metal layers for the SoC
  • The flexibility of integration to avoid congestion, IR-Drop or critical paths (rotation, accessibility of data, routability, abutment of the memory)

 

A PROCESS OF CONTINUOUS INNOVATIONS FOR AN OPTIMAL ACCURACY OF THE IN-SOC MEMORY AREA EVALUATION

  Logos A Logos B release 1 Logos B release 2
Goal Fast selection between the 2 metal layers options for Haumea according to the SoC characteristics Fast and fair area-based selection between 2 competitive memories Fast and fair area-based selection between 2 competitive memories
Means Measurement of the comparative in-SoC area of sRAM Haumea 1P3M and 1P4M Measurement of the comparative in-SoC area of 2 competitive 1P4M memories. Measurement of the comparative in-SoC area of 2 competitive 1P4M memories.
Content 8 Instances 2kx32 placed as 2 memory banks + logic block 8 Instances 2kx32 placed as 2 memory banks + logic block 8 instances for a total capacity depends on the selected benchmark placed as 2 memory banks
Measurement Memory area + abutment Memory area + abutment Memory area + abutment + routability on the top metal of the memory

 

KEY BENEFITS OF LOGOS

  • Easy area estimation
    • 30 minutes needed to obtain the results from evaluation
  • Make a decision based on reliable results regarding density
    • In-SoC area comparison
  • Several benchmarking contexts
    • For an optimal representativity
  • Support from Dolphin Integration
    • Guidelines for an easy evaluation
    • Engineering support to perform the evaluation if needed

 

LOGOS ASSESSMENT OF THE IN-SOC AREA OF MEMORIES: A FIRST EXAMPLE

Figure 1: LOGOS for competitors’ memories

competitors's memories

Densest competitor’s memories at ViC level require routing channels between the memories in order to access to the I/O pins resulting in higher area at SoC level.

Figure 2: LOGOS for Haumea

multiple access

Multiple access zones ensure data and power accessibility BOTH on the sides and over the memory. The better routability of Haumea allows to overcompensate, at SoC level, the area overhead at Virtual Component level.

 

DELIVERABLES

  • LOGOS evaluation Kit is composed of:
    • Tutorial
    • Scripts to automate the P&R of the memory banks
  • Evaluation process:
    • Licensor and user must first choose and agree with the complete LOGOS standard.
    • Licensor and user must adopt one benchmarking context: process, technological node, number of metal layers, memory capacity, timing constraints, floorplan…
    • Each party then completes the evaluation for assessing the in-SoC area achievable with its memory.
    • Both parties compare the reported data.

 

Figure 3: LOGOS block diagram

LOGOS block diagram