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Presentation Sheet

sROMet BCD HAUMEA rel 1.1 - generator 65LP

PRELIMINARY

 

Low fabrication costs
Low Power
Patented

patented

The Haumea architecture results from a three-pronged architectural innovation enabling:

  • The simultaneous generation of RAM and ROM instances.
  • The same optimizations for both RAMs and ROMs.
  • An optimization differentiated by instance.

Haumea at 65 nm LP represents the Best mix for Consumption and Density (BCD). It thus addresses both the needs of applications optimized for area and the needs of applications optimized for dynamic power, such as portable applications.
As for speed, it satisfies the needs for designs around standard processors.

 

Key features

  • Ultra low dynamic power
    Decrease of packaging cost
    Smaller SoC area
  • Decrease of fabrication costs
    Via metal 1-2 programmable ROM
    SoC routing allowed upwards from Metal 3
    Patented High Density bit cell
    Rotatable memory
  • Decongestion
    Multiple access zones replacing access points
    Innovative connection flexibility
    High routability over the ROM
  • Low-leakage
    no leakage in memory plane
    minimal leakage in memory periphery
  • Optimal DfY
    Read margin optimized instance by instance
schema

 

positionning

 

Optional ADD-ONS and PERIPHERALS

Scrambling
A scrambling feature customized for each user according to specific needs: it may include various protection structures involving addressing systems for word-lines, bit-lines, memory bit-cells…

Error Correcting Code
Our ECC generator is based on the HAMMING algorithm which enables to detect two errors and correct one error per word.

 

Flexibility

Generator flexibility
Min
Max
Granularity
Memory Bit Capacity
16 k
512 k
NA
Number of Words
2 k
16 k
512
Number of Bits per Word
8
32
2

 

 

Performances in following conditions for 65 nm LP

  • with SVt transistors and Dolphin’s High Density Bit-cell
  • Our architecture guarantees fabrication yield with a read margin optimized instance by instance
  • Voltage range is 1.2V +/-10%

To get access to the performances of this product, please fill in the following registration

 

Deliverables
socRouting
  • Specifications
  • Simulation models (VHDL/Verilog)
  • Abstract file (LEF)
  • Layout (GDSII)
  • Validation plan
  • Integration guidelines
  • Transistor netlist (CDL)
  • Synthesis model (.lib)
  • Data Sheet
  • Test vectors
  • User’s Guide and Install Note

Options: CCS views

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