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Presentation Sheet

SpRAM BCD HAUMEA rel 1.1 - generator 65LP

PRELIMINARY

 

Low fabrication costs
Low Power
Patented

patented

The Haumea architecture results from a three-pronged architectural innovation enabling:

  • The simultaneous generation of RAM and ROM instances.
  • The same optimizations for both RAMs and ROMs.
  • An optimization differentiated by instance.

Haumea at 65 nm LP represents the Best mix for Consumption and Density (BCD). It thus is designed around foundry bit cells and it addresses both the needs of applications optimized for area and the needs of applications optimized for dynamic power, such as portable applications.
As for Speed, it satisfies the needs for designs around standard processors.

 

Key features

  • Ultra low dynamic power
    Innovative design to minimize power consumption
    Decrease of packaging cost
    Smaller SoC area
    Optional Byte mode for Read operations
  • Decrease of fabrication costs
    1P3M with routing allowed upwards from Metal 3
    or 1P4M with M4 partially available for routing
    Rotatable memory
    High density memory
  • Decongestion
    Multiple access zones replacing access points
    Innovative connection flexibility
    High routability over the RAM
  • Low-leakage
    Data retention mode to switch off the periphery for inactive memory
  • Optimal DfY
    Read margin optimized instance by instance
schema

 

positionning

 

- Available modes -

Data Retention mode - included
For ultimate leakage savings: only the memory plane and the circuitry for retention would remain powered. Note that this data-retention mode requires 2 VDD power supply lines and one GND.

Byte mode - included
For more flexibility towards ultimate power savings, the capability of Byte-mode can be implemented in the RAM for Read/Write operations.

BIST - optional
The most efficient testing solution for industrial fabrication test of instances

 

Generator Flexibility

Form factors
Min
Max
Granularity
Memory Bit Capacity
16 k
512 k
NA
Number of Words
2 k
16 k
512
Number of Bits per Word
8
32
2

 

 

Performances in following conditions for 65 nm LP

  • with 6T HVt UHD TSMC Bit-cell reference T-N65-CL-CL-001
  • Our architecture guarantees fabrication yield with a read margin optimized instance by instance
  • Voltage range is 1.2V +/-10%
  • Typical case conditions: TT, 1.2 V, 25°C with the so-called “Pessimistic benchmark” for dynamic consumption and “Green RAM benchmark” for leakage in Data rentention mode

To get access to the performances of this product, please fill in the following registration

 

 

Deliverables
socRouting
  • Specifications
  • Simulation models (VHDL/Verilog)
  • Abstract file (LEF)
  • Layout (GDSII)
  • Validation plan
  • Integration guidelines
  • Transistor netlist (CDL)
  • Synthesis model (.lib)
  • Data Sheet
  • Test vectors
  • User’s Guide and Install Note

 

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