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Presentation Sheet

1PRFile BDS Aura generator 65 LP

PRELIMINARY

 

High Speed
High Density
Perfect match with HS-BTF

 

 

schema

For speed optimized applications like high speed consumer (gaming or DTV for example) and some mobile devices like advanced cell phones, the speed of the processor is dependant on performance of the memory and of the standard cell library. General purpose Silicon IPs in LP process do not satisfy the needs of high speed processors. To provide a solution for these applications, Dolphin Integration proposes a complete library optimized for high speed with the objective to meet performance requirements of any processor:
The HS-BTF Reduced Cell Stem Library enables to increase the speed limit of any processor
The One Port Register File Aura architecture (1R1W) optimized for high speed and high density can be ideally used for example as a cache memory to benefit fully of the performance capability of speed optimized processors. The Aura generator is available at a voltage of 1.2 V +/-10% and a Dual Voltage release is under development.


 

Positioning & Differentiators

positioning & differentiators

Key Benefits

  • Innovative architecture
    • Small capacity instances
    • Wide flexibility for words and bits per word
  • Ultra high speed
    • Up to 600 Mhz in worst case
  • Decrease of fabrication costs
    • High density memory
    • Designed with the uHD TSMC bit-cell
    • Metal 5 and above free for routing
  • Low leakage
    • Availability in LP process
    • Data retention mode to switch off the periphery for inactive memory
  • Optimal DfY
    • Read margin optimized instance by instance

 

 

- Available modes -

Byte mode - included
For more flexibility towards ultimate power savings, the capability of Byte-mode can be implemented in the RAM for Write operations.

BIST - optional
The most efficient testing solution for industrial fabrication test of instances

 

Flexibility

Generator Flexibility
Min
Max
Granularity
Memory Bit Capacity
128
32 k
NA
Number of Words
4
1 k
2
Number of Bits per Word
8
128
2

 

 

Performances in following conditions for 65 nm LP

  • with 6T SVt UHD TSMC Bit-cell reference T-N65-CL-CL-007
  • Our architecture guarantees fabrication yield with a read margin optimized instance by instance
  • Voltage range is 1.2 V +/-10%

 

 

Deliverables
socRouting
  • Specifications
  • Simulation models (VHDL/Verilog)
  • Synthesis model (.lib)
  • Abstract file (LEF)
  • Data Sheet
  • Transistor netlist (CDL)
  • Layout (GDSII)
  • Test vectors
  • Validation plan
  • User’s Guide and Install Note
  • Integration guidelines

 

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