Communication
Contacts
Offering
Investors
Careers
Sesame
Embedded memories
Logic virtual components
Analog virtual components
Test structures
Hardware/Software Codesign
Virtual test & diagnostic
Hardware/Software Codesign
Layout verification
Quadrant of skills
SoC Integration
Custom Fabless Supplier
 
 

Search dolphin:

silicium estimator
 
 

 

Presentation Sheet

spRAM eLCvHD PLUTON 180GP

 

 

extremely Low Power Consumption
very High Density

 

 

This single-port RAM, designed with the advanced PLUTON architecture and embedding the pushed-rule bit-cell from foundries, is the solution for low dynamic power consumption together with high density. Its variants offer solutions for multiple Byte-Write

 

 

Key features

  • Low Power
    • multi-plane architecture through the use of gated clocks and through the design with both micro-wordlines and micro-bitlines
      smart programming pulse circuitry to optimize the dynamic power consumed through read and write operations
  • Reduced Injection noise
  • High Density
    Pushed-rule bit-cell from foundry
  • High Yield
    Optimized for high DfY, i.e. no compromise at the cost of design margins
schema

 

positionning

ADD-ON

Error Correcting Code
Our ECC generator is based on the HAMMING algorithm which enables to detect 2 errors and correct one error per word.

Byte-Mux options
The Pluton Dual includes a Byte Mux feature for WRITING multiple Bytes at once; it is available at both soft (VHDL) and hard (GDSII) levels. It preserves low-power performance.

 

Dolphin’s RAM PLUTON offering

Would you need the low voltage capability of this memory, just request for the single-port SpRAM eLVvHD PLUTON 180GP operating from 2 V down to 1 V.

 

Flexibility

Generator flexibility
Min
Max
Granularity
Memory Bit Capacity
512
512 K
NA
Number of Words
128
65536
1
Number of Bits per Word
4
64
1

 

Performances in following conditions for 0.18 μm GP

  • Generic transistor option with 6T HD TSMC Bit-cell (ref. T-018-ES-CL-001 rev 1.3)
  • Typical case conditions: TT, 1.8 V, 25°C with “Pessimistic benchmark” for Dynamic consumption (100% active cycle)
  • Our architecture guaranties fabrication yield with the read margin larger than -10% of the effective power supply

To get access to the performances of this product, please fill in the following registration

 

 

Pluton Dual With Byte Mux option

 

 

Deliverables
socRouting
  • Specifications
  • Simulation models (VHDL/Verilog)
  • Timing files (TLF)
  • Synthesis model (.lib, .db)
  • Abstract file (LEF)
  • Data Sheet
  • Transistor netlist (CDL)
  • Layout (GDSII)
  • Test vectors
  • Validation plan
  • User’s Guide and Install Note
  • Integration guidelines

 

< 0.18 μm RAM Products
< Complete Offering RAM Products