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Presentation Sheet

1PRFile BDS Aura generator TSMC 180 nm G

PRELIMINARY

 

High Speed

High Density

Part of Symphonie Panoply

 

 

Fabless and Integrators of SoCs targeting the 180 nm G process can take advantage of Dolphin Integration’s Panoply enabling the generation of instances from 1 bit up to 1024 kbits. The Panoply includes:

  • Synthetisable instances with the High Density Standard Cell Library, SESAME uHD-BTF.
  • Generated instances with the 1PRFile Aura architecture optimized for high speed and density for medium capacities.
  • Generated instances with the SPRAM Pluton architecture optimized for low dynamic power and density for largest capacities.
  • Generated instances with the Dual metal programmable dROMet Cassiopeia optimized for low dynamic power and density.

For speed optimized applications like high speed consumer (gaming or DTV for example) and some mobile devices, General purpose Silicon IPs do not satisfy the needs of processors. To provide a solution for these applications, Dolphin Integration proposes the One Port Register File Aura architecture (1RW) optimized for high speed and high density. The Aura generator is available at a voltage of 1.8 V +/-10%.
The availability of two advanced releases of Aura is pending:

  • A Dual Voltage variant.
  • A Dual Port variant.

 

Key Benefits

  • Innovative architecture
    • Small capacity instances
    • Wide flexibility for words and bits per word
  • Ultra high speed
    • Up to 220 Mhz in worst case
  • Decrease of fabrication costs
    • High density Register File
    • Metal 5 and above free for routing
  • Optimal DfY
    • Read margin optimized instance by instance
 schema

 

 

 

POSITIONING & DIFFERENTIATORS

positionning

 

- Available modes -

Byte mode - included
For more flexibility towards ultimate power savings, the capability of Byte-mode can be implemented in the RAM for Write operations.

BIST - optional
The most efficient testing solution for industrial fabrication test of instances

 

Flexibility

Generator flexibility
Min
Max
Granularity
Memory Bit Capacity
128
32 k
NA
Number of Words
4
1 k
2
Number of Bits per Word
8
128
2

The flexibility of the Aura generator can be extended to the low-end with RTL coded implementations of register sets from the SESAME standard cell Library. FIFO and LIFO are available on request.

 

Performances in following conditions for TSMC 180 nm G

  • with 6T SVt UHD SMIC Bit-cell
  • Our architecture guarantees fabrication yield with a read margin optimized instance by instance
  • Voltage range is 1.8 V +/-10%

 

Deliverables
socRouting
  • Specifications
  • Simulation models (VHDL/Verilog)
  • Synthesis model (.lib)
  • Abstract file (LEF)
  • Data Sheet
  • Transistor netlist (CDL)
  • Layout (GDSII)
  • Test vectors
  • Validation plan
  • User’s Guide and Install Note
  • Integration guidelines

 

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