Presentation Sheet sROMet LCL CASSIOPEIA generator 130 LP     Low fabrication costs Low Power Low Voltage   Reducing the overall power consumption of a SoC is a critical issue for SoC designers, especially for portable applications. To address the needs of low power SoCs, Dolphin Integration has developed the Cassiopeia architecture for ROM. Cassiopeia enables low voltage operations at 130 nm thanks to its capability to operate at 1.1 V. CASSIOPEIA showcases a perfect mix between ultra-low power consumption and good density and speed. Key Benefits Ultra low dynamic power Innovative design to minimize power consumption Decrease of packaging cost Smaller SoC area Functionality down to 1.1 V Dynamic power consumption is significantly reduced Battery-life increases Decrease of fabrication costs High Density based architecture Single via programmable ROM Low leakage no leakage in memory plane minimal leakage in memory periphery Optimal DfY Read margin optimized instance by instance Optional add-ons and peripherals Scrambling A scrambling feature customized for each user according to specific needs: it may include various protection structures involving addressing systems for word-lines, bit-lines, memory bit-cells… Error Correcting Code Our ECC generator is based on the HAMMING algorithm which enables to detect two errors and correct one error per word.   Flexibility Generator flexibility Min Max Granularity Memory Bit Capacity 1 k 1024 K NA Number of Words 256 128 K 1 Number of Bits per Word 4 128 1   Performances in following conditions for 130 nm LP with SVt transistors and Dolphin's High Density Bit-cell Our architecture guarantees fabrication yield with a read margin optimized instance by instance Voltage range is 1.5 V +/-10% and 1.1 V +/-10% To get access to the performances of this product, please fill in the following registration   Deliverables Specifications Simulation models (VHDL/Verilog) Synthesis model (.lib) Abstract file (LEF) Data Sheet Options CCS views Transistor netlist (CDL) Layout (GDSII) Test vectors Validation plan User’s Guide and Install Note Integration guidelines   < 130 nm ROM Products < Complete Offering ROM Products

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