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Presentation Sheet

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SpRAM uLL NEPTUNE 130LL UMC

PRELIMINARY

 

ultra Low Leakage

 

 

Embedding two key patents, the Single-Port RAM-uLL Architecture is THE optimal mix between ultra low Leakage, low Dynamic Power consumption and Voltage Scaling.
It stars the proprietary architecture NEPTUNE-XAM:

  • the patented XAM bit-cell for minimizing dynamic power consumption
  • the «Thick and Thin » patent for leakage
  • the Self-sequenced circuitry for ensuring robustness against process deviations.

 

Key features

  • Ultra-low-leakage even in generic process
  • Data retention mode for switching off the peripheral logic when the memory is in sleep mode, for data retention, thanks to 3 power supplies (2 VDD, 1 GDS).
  • Functionality from 3.3 V down to 1.4 V for memory plane (Vdd33 core) & 1.2 V for peripheral logic (Vdd12 in) leading to 30% power savings compared to operating at 3.3 V
  • Low-power consumption
  • Optimal high DfY
schema

 

positionning

 

ADD-ON KIT (optional functionsl)

Byte-write mode

For more flexibility towards ultimate power savings, the capability of writing per single, double or quadruple Bytes can be implemented in the RAM

  

Error Correcting Code

Our ECC generator is based on the HAMMING algorithm that enables to detect two errors and correct one error per word.

  

A DC-DC Converters

is provided for a single power supply VDD12 as voltage-doubler add-on, but mode control maintains VDD33 between 0.9 and 1.32 V in power-down mode.

BIST for decreasing the cost of the industrial test

 

Reliability & Robustness

RagTime generators benefit from unique design & validation methods which ensure high robustness over process variation and reliability upon SoC integration:

  • patented design immunity against process deviations, as self-sequenced circuitry…
  • Stringent check-out with (1) over stressed conditions, (2) electro-migration assessment, (3) evaluation of sensitivity against device mismatch, (4) accurate modeling and simulation for monitoring peaks of current…
  • Safe Read-margins, corner lot and worst-case qualification through our Virtual Fab Process™

 

Flexibility

Generator flexibility
Min
Max
Granularity
Memory Bit Capacity
8 kbits
256 Kbits
NA
Number of Words
512
16 384
1
Number of Bits per Word
8
64
1

 

Performances in following conditions for 0.13 µm LL (UMC)

  • Transistor options: generic and 3.3 V with 6T patented XAM Bit-cell and «Thick and Thin » patent for leakage in Data Retention mode
  • Worst case conditions for timings SS, 25°C, VDD12 = 1.08 V, VDD33 = 3.0V
  • Worst case conditions for dynamic power consumption FF, -40°C, VDD12 = 1.32 V, VDD33 = 3.6V
  • Typical conditions for leakage TT, 25°C, VDD12 = 0 , VDD33 = 0.9 V
  • Our architecture guaranties fabrication yield with a read margin larger than 10% of the effective power supply

To get access to the performances of this product, please fill in the following registration

 

Deliverables
socRouting
  • Specifications
  • Simulation models (VHDL/Verilog)
  • Synthesis model with timing and power data (.lib)
  • Abstract file (LEF)
  • Data Sheet
  • Transistor netlist for LVS purpose (CDL)
  • Layout (GDSII)
  • User’s Guide and Install Note
  • Integration guidelines

 

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