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Presentation Sheet

SpRAM-uLCeLL URANUS 130G

 

 

ultra Low Power

extremely Low Leakage

 

The worth of a Single-Port RAM within a SoC depends on the optimization goal of the Integrator: URANUS is the ultimate winner with "(ultra) Low power Consumption (extremely) Low Leakage and (very) High Density" to enable traveling with portable devices which demands the combination of Low Power, High density and Low Leakage.

High density of bit cells was the traditional provider of Low dynamic power, but Low Leakage now is its preferred companion and the Data Retention mode enables their ultimate savings!

 

 

Key features

  • Low Power consumption
    Innovative design with low power reading circuitry enables to minimize power consumption
  • Low Leakage
    Ultimate leakage savings thanks to Data Retention mode that enables to switch off the periphery when the memory is not active
  • High Density
    Pushed-rule for Ultra High Density bit-cells with the same performances as a standard bit-cell
  • Optimal DfY
    No compromise with design margins: no drop of yield
schema

 

positionning

 

- Available modes -

Power-down mode - included

For ultimate leakage savings: only the memory plane and the circuitry for data retention would remain powered. Note that this Data Retention mode requires at least 3 power supplies (2 VDD, 1 VSS).

Byte-write mode - optional

For more flexibility towards ultimate power savings, the capability of writing per Byte can be implemented in the RAM.

 

Flexibility

Generator flexibility
Min
Max
Granularity
Number of Words
128
8 k
1
Number of Bits per Word
8
64
1
Memory Bit Capacity
1 k
512 k
NA

 

Performances in following conditions for 130 nm G (TSMC)

  • with SVt 6T UHD Bit-cell (ref. T-013-ES-CL-004)
  • Typical case conditions: TT, 1.2 V, 25°C with the so-called “Pessimistic benchmark” for dynamic consumption (100% active cycle), “Green RAM benchmark” for leakage in Data Retention mode.
  • Our architecture guaranties fabrication yield with a read margin larger than 10% of the effective power supply.
  • Voltage range is 1.2 V+/- 10 %.

To get access to the performances of this product, please fill in the following registration

 

Deliverables
socRouting
  • Specifications
  • Simulation models (VHDL/Verilog)
  • Synthesis model (.lib, .db)
  • Abstract file (LEF)
  • Data Sheet
  • Transistor netlist (CDL)
  • Layout (GDSII)
  • Test vectors
  • Validation plan
  • User’s Guide and Install Note
  • Integration guidelines

 

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