I-Stratus-LP Dynamically self-configured Cache Controller
Preliminary
Minimized power consumption |
Self-configurable for an
adaptative optimization |
Fastest Time-To-Market |
Historically, designers have always thought of a Cache as a means for improving the speed of a system but now, power consumption issues have to be addressed. Furthermore, the major challenge for using conventional cache controllers is the strong dependence of their performances on the application program. It implies to carefully configure the cache controller based on some assumption on the average behavior of the application program. However, such a fixed configuration will only result in average speed and power consumption.
To remove this bottleneck, I-Stratus-LP - Level 1 instruction cache controller provides a breakthrough functionality: a dynamic and automatic configuration of its parameters. It ensures the lowest power consumption together with an increase of performance while enabling an easy set-up of the cache controller.
Example of a system using an Instruction Cache and an external Flash memory as program memory. Key benefits
-
Power consumption reduced up to 10 times compared to a usual cache controller and up to 8 times compared to a cache-less system
- The Dynamic self-configuration enables to fit to each variation of the application program, and thus ensures an adapted minimized power consumption
-
Higher processing power than a cache-less memory
-
Easy set-up to minimize the integration costs: thanks to the self-adapted configuration to the application program content
- One Stratus cache controller fits multiple SoC requirements and any application program
- No need to acquire some specific knowledge on how to configure a cache controller
- No need to wait for the application program for configuring the best cache solution
Fixed features
-
Replacement policy: cyclic
-
Support of a wide range of external memories of 8 or 16 bits with an AXI compatible interface: NOR Flash, MRAM, ROM, SRAM, etc.
Self-configured features
-
Direct map, 2-way or 4-way set associative
-
Cache line size: 8, 16 or 32 words
Parameters to select before the delivery
-
Cache memory capacity: 4 kB, 8 kB, 16 kB, 32 kB
-
Data bus size, according to the MCU: 8, 16 or 32 bits
-
Addressable content of the background memory: up to 4 GB
What gains thanks to I-Stratus-LP?
| Improving your solution with I-Stratus-LP |
Reduction of power consumption |
Acceleration of average memory access time |
Area savings |
Reduced Time To Market |
Reuse |
| external memory (e.g. Flash, EEPROM) + embedded local memory (RAM) replaced by an External memory + I-Stratus-LP |
YES
Minimum: 5%
Maximum: 30% |
=
(Similar average access time) |
YES
Area of the cache system < area of the embedded RAM |
YES |
YES
In different SoCs & with different application programs, without the painful step of finding the best configuration for each project |
| embedded memory (e.g. Flash, ROM) + I-Stratus-LP |
YES
Minimum: 30%
Maximum: /5 |
YES
Minimum 20% |
NO
Increase of the cache memory capacity (for a 4kB @ 0.18: 0.3mm2) |
YES |
| embedded memory (e.g. Flash, ROM) replaced by an External memory + I-Stratus-LP |
YES
Minimum: 50%
Maximum: /10 |
YES
Minimum 20% |
YES
Drastic reduction from the large memory to the size of the cache system |
YES |
| conventional cache replaced by I-Stratus-LP |
YES
Minimum: 30%
Maximum: /3. |
=
(Similar average access time) |
=
(Same area) |
YES |
The dynamic self-configuration enables
to target an optimized power-consumption for each part
of any application program, which is not feasible with a usual
configurable cache
Step by step adaptation, for reducing development costs
Deliverables
-
Solution
-
I-Stratus-LP RTL Verilog + specifications
-
Testbench and patterns tests
-
Timing constraints
-
User guide
-
TAG and Cache memories (optional)
< Peripherals Overview
|
