| |
Flip 8051 |
Flip 80251 |
Flip APS32 |
Instruction Set |
Full binary code compatibility with the legacy 80C51/80C52 |
Upward compatibility with 8051 microcontrollers
Enriched C51 instruction set (native mode):
16-bit & 32-bit arithmetic and logic instructions |
16 and 32-bit long instructions for superior code density with no mode switch |
Architecture |
A pipelined architecture enables to reduce the number of clock per instruction |
A 4-stage instruction pipeline enables to execute most of the instruction in a single cycle |
Pipeline Harvard architecture with completion of out-of-order instructions (memory latency hiding) |
Addressing Space |
64 Kbyte linear addressing space
Extension up to 4Mbyte with code banking |
16 Mbyte linear addressing space |
4 Gbyte linear addressing space |
Performances Dhrystone v2.1 / 200 loops |
Wind: 0.026 DMIPS/MHz
Cyclone: 0.074 DMIPS/MHz
Whirl-Cyclone:
Cyclone + 16 DSP instructions |
Typhoon: 0.296 DMIPS/MHz
Hurricane: 0,4 DMIPS/MHz |
APS32: 1.15 DMIPS/MHz (without divide module); 1.67 DMIPS/MHz (with optional HW divide module) |