IP Core: From Flip 8051 to Flip 80251 and APS-32 The Rock’n Roll products line of Dolphin Integration provides a full range of controllers with different processing power. 8/16/32-bit CPU will permits to choose the best trade-off for each application. All Dolphin’s controllers are developed for low power consumption. Moreover, they target control applications thanks to an optimized instruction set (e.g. bit manipulation instruction for 80x51) and fast interrupt handling. Our CPU can be associated with instruction/data cache controllers which enable to improve the interface with external memory (e.g. Flash), providing a way to optimize either the system performance or to reduce the power consumption. Dolphin provides the most efficient Software Development Platforms from the now celebrated Flip8051 up the compatibility ladder. It comprises the vital capability of a complete Station PRIDE™, "Panoply for Retargeting under an Integrated Development Environment", for migrating complex Software Applications upwards: these ultimately require the large addressing capability of a 32-bit architecture, even beyond the optimum ratio of performance per area, especially for the data bases at advanced technological nodes.   News Corner I-Stratus-LP, the Cache Controller for cooling memory access May 20, 2011 - The art of embedding Non-Volatile Memories renewed by Dolphin Integration's Cache March 11, 2011 - BIRD Owl, the new real-time debugging solution for the 16-bit microcontrollers Dec. 03, 2010 - The new real-Time debugging solution Sept. 24, 2010 - The first 16-bit MCU core 8051 upward compatible, achieving 0.4 DMIPS/MHz more news…   8-bit /16-bit /32-bit IP Core for system control, when peripherals management is required PRIDE development platform for emulating and debugging applications software     Main Characteristics and Performances of Microcontrollers   Flip 8051 Flip 80251 Flip APS32 Instruction Set Full binary code compatibility with the legacy 80C51/80C52 Upward compatibility with 8051 microcontrollers Enriched C51 instruction set (native mode): 16-bit & 32-bit arithmetic and logic instructions 16 and 32-bit long instructions for superior code density with no mode switch Architecture A pipelined architecture enables to reduce the number of clock per instruction A 4-stage instruction pipeline enables to execute most of the instruction in a single cycle Pipeline Harvard architecture with completion of out-of-order instructions (memory latency hiding) Addressing Space 64 Kbyte linear addressing space Extension up to 4Mbyte with code banking 16 Mbyte linear addressing space 4 Gbyte linear addressing space Performances Dhrystone v2.1 / 200 loops Wind: 0.026 DMIPS/MHz Cyclone: 0.074 DMIPS/MHz Whirl-Cyclone: Cyclone + 16 DSP instructions Typhoon: 0.296 DMIPS/MHz Hurricane: 0,4 DMIPS/MHz APS32: 1.15 DMIPS/MHz (without divide module); 1.67 DMIPS/MHz (with optional HW divide module)

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