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Flip 8051 |
Flip 80251 |
APS3 |
Instruction Set |
Full binary code compatibility with the legacy 80C51/80C52 |
Upward compatibility with 8051 MCUs Enriched C51 instruction set for a better support by C-compiler |
16 and 32-bit long instructions for superior code density with no mode switch |
Architecture |
A pipelined architecture enables to reduce the number of clock per instruction |
A 4-stage instruction pipeline enables to execute most of the instruction in a single cycle |
Pipeline Harvard architecture with completion of out-of-order instructions |
Linear Addressing Space |
64 Kbyte
Extendable up to 1 MByte with code banking
|
16 Mbyte |
4 Gbyte |
Performances – DMIPS/MHZ
Dhrystone V2.1 / 10,000 Loops
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Wind: 0.035
Cyclone: 0.08
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Typhoon: 0.22
Hurricane: 0.34
Tornado: 0.58 |
APS3R: up to 2.29 (with optional HW divide module) |
Debug solution |
BIRD Tiny, BIRD Advanced
SUCCESS |
BIRD Owl TNY, BIRD Owl STD SUCCESS |
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