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Microcontroller Differentiators
Benefits for Power Consumption |
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Lower frequency yields lower power consumption |
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Efficiency in power consumption when providing the same computing power:
FlipAPS32 can reduce drastically power consumption compared with any microcontroller with the same computing power, and could flag even more impressive power savings when combined with the celebrated low power library, SESAME.
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The required processing power can be obtained at a lower frequency thanks to the FlipAPS32, when compared to 8/16-bit architecture, thus enabling to reduce the power consumption, not only for the core itself, but for the program and data memories.
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SoC-Level Cost
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Thanks to Flip80251 architecture, the size of the compiled code can be reduced up to 46% when compared to the 80C51!!
With FlipAPS32, the gain is up to 25 %.
The code density impacts the program memory capacity and, as a consequence, it reduces the “core + memory” area. |
Area savings
 When comparing the silicon area of Flip80251 Typhoon or Flip80251 Hurricane + its program memory (located in RAM) versus the silicon area of Flip8051-Cyclone in the same configuration, area savings reach up to 41 %, thanks to the program memory.
With the same comparison between Cyclone and FlipAPS32, area savings reach up to 28.5 %.
Processing power
Flip8051
0.009 DMIPS/MHz
(same power as i8051) |
→x 4 → |
Flip8051 Wind
0.036 DMIPS/MHz |
→x 2.4 → |
Flip8051 Cyclone
0.085 DMIPS/MHz
(‘1T’) |
→x 13.5 → |
FlipAPS32
1.15 DMIPS/MHz
Higher Processing
Power |
→x 6.9 → |
Flip80251 Hurricane
0.59 DMIPS/MHz
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→x 3.5 → |
Flip80251 Typhoon
0.296 DMIPS/MHz
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Processing power is based on Dhrystone 2.1
| Acceleration of your Application program |
By 3
to 9-times, and up to 300-times with the DSP
instructions |
| Reduction of the SoC power consumption |
By 30%, 50%, 60% or more with the CPMU
and the ECPMU |
| Reduction of the CPU Silicon Cost |
By customization of Processor and Controller area
with configurable
peripherals |
| Reliability and robustness for your SoC |
Thanks to the adaptativeness of the Virtual
Testbench for each configuration |
| Protection against Accesses to Memories |
SoC Anti Piracy
with respect to any emulator interface |
| Reduction of your SoC development costs |
With optimized software
tools for code development, low-cost patented ICE
solutions for application program debugging and codesign on cosimulator
SUCCESS. |
| Roadmap for Future SoC generation |
With on-going innovations
improving all the above for a lasting partnership |
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