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Best with... ultra Low Leakage

The Dolphin bundle at 0.13 µm optimized for ultra-low-leakage

Microcontroller & peripherals
Standard Cell Library
Memories

 

“Leakage power” has definitely become the cool criterion for optimizing applications operating during some microseconds per hour and targeting a battery-life longer than a year.
Hot applications: RFID, ZigBee, intelligent mesh networks, and generally all the portable applications requiring low-leakage.
Last but not least… our patented solutions are wisely designed for enabling leakage savings for very deep submicron process technologies!

 

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The breakthrough innovation enables leakage savings down to 1/100 over traditional designs at 0.13 µm node, starring Dolphin’s RAMs and standard cells, with a new standard, benefiting from a patent named “Thick’n Thin.

But… what about embedding our ultra-low-leakage late-programmable ROM as well, and our microcontroller 8050-CYCLONE-LL synthesized, placed and routed with this standard-cell library optimized for ultra-low-leakage?

Let’s discover now in more detail the four Virtual Components comprising the Dolphin’s bundle

 

Single-Port RAM NEPTUNE-XAM

 

sROMet-uLC CASSIOPEIA
Standard Cell Library: SESAME uHVuLL
Microcontroller: 8050-CYCLONE-hard-eLLvHD

Single-Port RAM NEPTUNE-XAM

PRELIMINARY

 

ultra Low Leakage

 

 

Embedding two key patents, the Single-Port RAM-uLL Architecture is THE optimal mix between ultra low Leakage, low Dynamic Power consumption and Voltage Scaling
It stars the proprietary architecture NEPTUNE-XAM:

  • the patented XAM bit-cell for minimizing dynamic power consumption
  • the «Thick and Thin » patent for leakage
  • the Self-sequenced circuitry for ensuring robustness against process deviations.

 

 

Key features

  • Ultra-low-leakage even in generic process
  • Power-down mode for switching off the peripheral logic when the memory is in sleep mode, for data retention, thanks to 3 power supplies (2 VDD, 1 GDS).
  • Functionality from 3.3 V down to 1.4 V for memory plane (Vdd33 core) & 1.2 V for peripheral logic (Vdd12 in) leading to 30% power savings compared to operating at 3.3 V
  • Low-power consumption
  • Optimal high DfY
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ADD-ON KIT (optional functionsl)

Byte-write mode

For more flexibility towards ultimate power savings, the capability of writing per single, double or quadruple Bytes can be implemented in the RAM

  

Error Correcting Code

Our ECC generator is based on the HAMMING algorithm that enables to detect two errors and correct one error per word.

  

DC-DC Converters are provided as add-ons to enable low voltage or voltage scaling, resulting in an increase of the battery-life for portable devices

BIST for decreasing the cost of the industrial test